Electronic Design
JTAG And IDE Ramp Up Arm Multicore Support

JTAG And IDE Ramp Up Arm Multicore Support

IAR has delivered some impressive development tool enhancements in the past including power debugging for Arm processors (see IAR Debugger Finds Power Hot Spots). The new JTAGJet-Trace (Fig. 1) is integrated with the IAR Embedded Workbench for Arm to handle Arm's Cortex-M, Cortex-R and Cortex-A devices. It can also handle older chips based on the ARM7/9/11 architectures.

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Figure 1. IAR's JTAGJet-Trace is integrated with the IAR Embedded Workbench for Arm and supports the full trace capabilities of Arm's Cortex-M, Cortex-R and Cortex-A devices in addition to ARM7/9/11 architectures.

The JTAGJet-Trace provides JTAG debug support but it also supports Arm's Embedded Trace Macrocell (ETM). It can perform trace acquisition with a trace clock rate up to 200MHz that equates to 400Msample/s from the ETM. The unit has a trace buffer capture capacity up to 18 Mbytes. Data and clock skew are minimized through the use of auto-adjust timing support. Each entry has a 56-bit time stamp that provides a CPU cycle accuracy down to 5ns.

Time stamping allows the IAR Embedded Workbench to coordinate multiple cores in a multicore or system environment. This includes support for multiple serial wire debug (SWD) devices.

The IAR IDE also incorporates a number of improvements in addition to support for the JTAGJet-Trace. The C/C++ compiler has seen a 10% performance boost. The IAR Embedded Workbench C compiler already handles static analysis providing MISRA-C support (see Why Are You Still Using C?). Static analysis allows the IDE provide features like a call graph (Fig. 2) for easier navigation of code from an application architectural standpoint.

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Figure 2. IAR Embedded Workbench now incorporates a hierarchical call graph window making it easier to analyze an application.

The IAR Embedded Workbench also works with IAR's visualSTATE tool. Developers can graphically design and develop state machines using visualSTATE. The tool generates compact C/C++ code.

The IAR Embedded Workbench supports a range of microprocessors in addition to the Arm architectures. A recent release supports Renesas' RX200 and Rx600 series. The tools are also compliant with the Renesas RX ABI and the assembler support matches the RX assembler. Power debugging is supported on the Renesas platforms as well.

The IDE also supports a new  License Management System (LMS). It supports features like commuter licensing and automatic license activation. It also supports virtual servers.

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