TimingDesigner 9.25 now includes enhanced Automerge functionality that decreases interface timing analysis time. The function enables a reusable, model-based approach to timing analysis. Users can quickly connect component timing models to create parameterized interface diagrams that are useable to validate timing and interactively test design alternatives. Release 9.25 also includes a number of updates to the Allegro PCB SI flow and more design validation commands to help users identify critical margins, ensure proper analysis, and determine when they have reached timing closure. Design Automation Inc., Rochester, NY. (800) 813-7494.