Just a couple of years ago, many designers struggled with bus and I/O speeds that continued to plod along while processors doubled their clock speeds every 12 to 18 months. Then, almost overnight, bus and I/O technology began to change. The speeds doubled, then doubled again. On top of that, new approaches like source-synchronous clocking—and the measurement challenges presented by the small data-valid windows of low-voltage differential signaling (LVDS)—have made measurement, verification, and validation more important than ever. Yet, the very same forces that bring such performance improvements also make the insertion of test equipment increasingly more intrusive.
The good news is that new tools and methodologies are available to minimize the impact on your design. However, careful planning for testing must now happen during the very initial stages of a design. It's no longer possible to build a prototype and then simply solder on some wires to connect a scope or logic analyzer. Your test methodology must be an integral part of your design plan.
Unfortunately, the techniques and tools that digital designers have used for years are no longer applicable. Today's designer wouldn't even think about designing a gigabit-per-second bus without extensive modeling and Spice simulations. Yet many of them continue to approach troubleshooting and debugging of these high-speed circuits with the same tools and methodologies implemented during the good old days of 4-MHz processors.
To achieve these breakthroughs in speed, such technologies as HyperTransport, InfiniBand, and RapidIO have adopted "new" electrical requirements like LVDS and replaced traditional multidrop buses with efficient point-to-point bus architectures. Suddenly, digital designers have been thrust from the comfortable world of ones and zeros into the high-frequency analog world. Those who attended their first class on fields and waves, and went screaming into the night, are being dragged back into the real-life classroom of transmission-line theory, reflections, and even S-parameters.
Because of the high-frequency effects and the new topologies of today's buses, designers need to more efficiently implement test equipment for determining signal integrity and data integrity. While simulation and emulation tools continue to mature and improve, the new bus technologies limit the usefulness of these tools.
For example, models are built over time from learning and observed behavior. When a new bus appears on the market, there's little information available to the majority of engineers. For the most part, leading-edge adopters of these technologies consider their knowledge intellectual property. They don't share this information until it becomes mainstream. So test tools, and the ability to employ them for debug and validation, are critical during early adoption.
With those old 4-MHz microprocessors—or the more recent USB 1.1 devices—a 100-MHz scope and any scope probe handy were more than enough. They could handle 1.5-Mbit/s or even 12-Mbit/s devices. Now, with 480-Mbit/s USB speeds, even a simple thing like an oscilloscope probe can dramatically impact your system's behavior.
How much more are your test-equipment measurement choices going to affect leading-edge systems, such as a HyperTransport link double-pumping data via a 1-GHz clock? Data capture is especially affected because of the reduction in setup-and-hold times. In fact, the emergence of new technologies has brought about new terminology. Setup-and-hold times are now passé terms. Now a high-speed data transfer is called a "data-valid window." This is a combination of setup, hold, and voltage swing.
Consider that in 1992, the Intel Pentium front-side bus (FSB) had a setup requirement of 5 ns and a voltage swing of 5 V. Today, the data-valid window for InfiniBand and RapidIO is 250 ps, with a differential voltage swing of 200 mV.
Compared to the 1992 Intel FSB, current InfiniBand specifications have a 20× reduction in the data-valid window and a 25× reduction in the voltage swing—a delta of 500. In other words, today's buses use only 0.2% of the energy that the 1992 Pentium FSB consumed.
The move from the traditional multidrop bus to a point-to-point topology creates another challenge. A perfect example of a multidrop bus is the PCI bus. With multiple connectors, snooping the bus was relatively easy. The test tool or test connection could be plugged into one connector, leaving other connectors available to plug the real devices into.
But the HyperTransport specification doesn't even contain one connector. How then can a designer snoop a bus? This challenge isn't limited to HyperTransport. With PCI-X at 133 MHz, there's only one slot. If a test tool is plugged in, the slot isn't available for use with a real device.
To date, the connection solution for PCI-X and Accelerated Graphics Port 2.0 (AGP 4X) has been an interposer design. This is a card that plugs into the connector on the motherboard, while providing a connector for an application device as well as a path to a logic analyzer. This solution requires extremely careful interposer design to prevent signal skew and loading of the target system.
The interposer design methodology works fine up to 133-MHz clock rates. It's even a very stable design for systems double-clocking the data, such as 266-megatransfer/s (MT/s) DDR SDRAM. However, as the technology makes the next leap to 533 MT/s and beyond, the interposer design becomes far too intrusive, creating loading, reflections, stubs, and unacceptable path delays.
A conundrum now exists. New technologies mean that simulations and models don't provide sufficient detail to have confidence in a product. Therefore, physical measurements are critical, yet simple links through connectors are no longer viable.
The following two examples show different ap-proaches to solving the connection challenge. One example looks at how to design in a connector for a HyperTransport link. The other examines an AGP3.0 port, where an interposer-style solution is no longer viable. Both were developed to enable the connection of analysis probes. In each case, designers performed extensive Spice simulations, as well as real-world physical verification to prove the validity and robustness of the connection solutions.
HyperTransport: An innovative, new serial-link interface, HyperTransport can transfer data at a theoretical speed of 16 Gbytes/s. The physical layer employs LVDS signaling technology with a voltage swing of 800 mV and has a data-valid window of 200 ps. As mentioned earlier, HyperTransport presents a unique challenge because it doesn't include any connectors. Without connectors, tracking problems to the root cause, capturing complex sequences, and validating the robustness of the system become difficult, if not impossible.
To access the HyperTransport link, a connector must be designed into the target system. The Spice models here show the values from the HyperTransport link specifications, an 80-pin Robinson Nugent connector, and the FuturePlus FS2240 HyperTransport analysis probe. This example is used for illustration purposes.
The FS2240 is designed to sample the signals between two HyperTransport devices. A probe connection is made for each unidirectional link. The 8-bit link comprises eight data, one control, and one clock signal, while the 16-bit link is composed of 16 data, one control, and two clock signals. The target design's HyperTransport signals are wired to the probe through isolating tip resistors. When the probe is attached to the target, it presents only a nominal load across each of the link's differential pairs.
With previous generations of embedded buses, the typical test solution has been for the designer to include a test connector in the board layout. At lower frequencies, the stubs that were created had a minimal impact on the bus. But at the frequencies of today's differential buses, stubs are unacceptable sources of reflections. A simple solution is to bridge the gap between the connector pads and the link with tip resistors. When the test connection is no longer required, just remove the tip resistors to eliminate any stub-related problems.
When it's time to progress from design to manufacturing, the tip resistors and connector just aren't loaded. Only the pads for the connector remain. There's a hidden benefit to taking this approach: If a product fails in the field, or a problem arises with an entire product family, it's very easy to connect to the bus and verify the operation. Simply load the connector and tip resistors, and the board will be ready for test.
To minimize the impact on the target HyperTransport link, the test connection must be carefully designed into the circuit. This is accomplished by using a Spice model as part of a circuit simulation. The correct tip-resistor values, connector placement, and trace lengths are critical to incorporating the connector and minimizing the impact on the link. The target design requirements are:
- Delays of signals from the driving device to the connector are equalized.
- The maximum etch length to the connector is limited.
- The stub length of the etch, from target signal to tip resistor, is minimized.
Figure 1 shows the recommended etch lengths from the driver to the Robinson Nugent connector. Note that the difference in trace lengths between the data links and the clock lines must be matched within ±0.02 in. Also, the trace length difference between the differential pairs is limited to ±0.02 in. Overall, trace length from the driver to the connector is defined as under 4 in.
To assist the designer in optimizing the design, the impedance values for the traces are identified as well. The minimum signal levels at the input side of the 226-Ω tip resistors should be 550-mV nominal, as per the HyperTransport specification. The values given are based on a clock frequency of 1 GHz. Longer trace lengths can be accommodated, if the clock frequency is lower than 1 GHz.
Predictions from a simulation show the signal behavior for a data line with no connector or tip resistors in the design (Fig. 2a) and with the connector and 226-Ω tip resistors added to the design (Fig. 2b). The scope-like waveforms reveal that adding the connector, 226-Ω tip resistors, and our analysis probe results in less than 7% signal reduction.
As with everything in engineering, this solution involves tradeoffs. It requires space on the board for the connector, including a keep-out area to allow mating of the FS2240 test-connector shell. One reason to select the 80-pin Robinson Nugent connector was its small size and high-frequency characteristics. By far, the largest tradeoff is the effort required to design in the connector.
Adding a test connector requires planning. Not thinking ahead could mean that you won't be able to test the circuit, or you will need to add a connector later on. The first situation can result in shipping a product that hasn't been fully characterized. In the second scenario, adding a connector can significantly delay product development. Like most things in life, a little planning at the beginning can save a great deal of time and money in the end.
AGP3.0: This generation calls for an 800-mV voltage swing, with data speeds of 266 MT/s (4X) and 533 MT/s (8X). The previous-generation AGP2.0 had a maximum data rate of 266 MT/s, but the voltage swing was 1.5 V. With a speed of 533 MT/s, a 50% reduction in voltage makes using an interposer with AGP 4X difficult, and maybe impossible.
Designing in another connector similar to what was done for HyperTransport would be very difficult given the nature of the AGP signals and the bus width. So we developed a unique probing solution that takes advantage of the existing PCI-style connector, while preventing the signal delays and loading that an interposer would introduce.
The connection solution is a flex/stiffened-flex pc board that's soldered directly to the backside (solder side) of the target's AGP connector. As Figure 3 shows, the probe adapter will contain the isolating tip resistors and connector for the probe's cable adapter, illustrated in Figure 4.
All components of the probe adapter are mounted on the side opposing the target. This enables flush mounting of the adapter to the target. Employing a flex circuit to attach to the connector maximizes the use of board space and maintains signal integrity. It also provides a connection system that can be used on production systems and prototype boards.
This solution necessitates a small component keep-out area near the target's AGP connector. Due to the increased density of new motherboards, this requirement may be difficult to implement for some production products. Additionally, the through-hole leads from the connector must be long enough for the flex circuit to solder to. Once the flex circuit is attached, it may be difficult to remove, without inadvertently damaging the probe adapter. Thus, for all practical purposes, the probe should be considered consumable.