Electronic Design

DFT Propels SoC IC Testing

The Design-for-Test (DFT) methodology is a strong driving force in the cost-effective testing of large-volume commodity items with very short life cycles, like system-on-chip (SoC) devices. It will remain that driving force, operating under the rubric of the IEEE P1500 Standard for Embedded Test (SECT) or ad-hoc core-integration strategies.

DFT's heightened use in SoCs has created a new type of instrument. It exploits the modularity that DFT brings to SoC testing based on a standardized approach. Without some sort of standardized or semi-standardized method of testing these devices, it would be almost impossible to create test programs for SoCs with a very short life cycle, as quickly as possible. Some of these devices are on the shelf for only six months before becoming obsolete. Without using a DFT methodology, one can easily spend more time creating tests for SoCs than designing them. For example, Teseda Corp.'s Validator 500 tool focuses on the validation and verification of the DFT functions and test data. It performs no functional testing, which is in the domain of very expensive system automatic test equipment (ATE systems). DFT lets you produce lower-cost testers.

For very high-end leading-edge designs, functional testing is more important. However, for those commodity large-volume consumer-oriented applications that use a well-characterized manufacturing process, DFT testing could be all you need. It's a lot easier to generate the tests, and it gets you into final production more quickly. Despite its advantages, functional testing is increasingly being "shoe-horned" into a quickly narrowing niche, causing us to rethink where it really is necessary.

Tesada's work in producing SoC core testers has run complementary to the work of the P1500 Standards Committee. P1500 may never be adopted, yet companies will—some already do—integrate cores. They must. P1500 would be a boon to the industry. Nevertheless, SoC design and DFT adoption will continue unabated. DFT is one form of "plumbing" to hook things together. It allows you to know more about the cores and the internal scan chains. You don't typically get this information in an ATE system.

Given the P1500 standard, more information will be developed on how to interconnect internal SoC circuitry. This, in turn, will help with things like debugging, first-silicon testing, etc. In the future, the company will look at the core test language (CTL), which allows things like core isolation. This option enables users to test a core while keeping the rest of the chip quiet. What's a very difficult task now will be simplified as more standards evolve within the P1500 specification.

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