An improved family of embedded test IP products delivers significant benefits to designers of systems-on-a-chip (SoCs) and other complex ICs. These products improve testing efficiency, speed, and accuracy. New capabilities include advanced memory, Test Access Port (TAP) and Boundary Scan capabilities, and logic functionality.
The memory embedded test algorithm for multiport RAMs has been enhanced to improve coverage of defects that cause interference between ports. In cases where the TAP is only required to manage chip-level test, test logic can be automatically inserted to enable sharing of functional pins with TAP pins.
Embedded test has been developed to overcome the external test barrier by automatically generating and incorporating proprietary microtest IP blocks into the IC at the design stage. These small blocks facilitate predictable, at-speed self-test and diagnosis of the IC during manufacture. This embedded circuitry can be used to efficiently test logic, memory, and mixed-signal functions. Testing is completed under the control of a five-pin IEEE 1149.1 test bus. Contact the company for pricing and availability information. lf
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