Unlike emulators that rely on bulkier and expensive external hardware pods, two new emulators, known as the ScanICE-ARC and NetICE-ARC, use the JTAG standard test access port to tap internal debug resources available on ARC Tangent processors. By eliminating the need for external hardware pods, the emulators, each of which include the MetaWare Windows 95/98/NT/2000 compatible SeeCode source-level debugger, reduce the cost and electrical loading of the target system. For JTAG emulation access, the ScanICE-ARC uses a PCI bus JTAG controller installed on a PC, while the NetICE-ARC uses a LAN-based (Ethernet) JTAG controller. Users can download programs and data to any part of the system RAM through the JTAG port without need for a resident loader program or ROM emulator. A standard four-wire JTAG interface allows the controller to connect to ARCÕs processor and any future processors developed by ARC. As an additional benefit, each of the JTAG controllers can be used in boundary-scan interconnect testing and in-system programming (ISP) of flash devices and CPLDs using ScanPlus boundary scan-test and ISP software. More details are available from CORELIS INC, Cerritos, CA. (562) 926-6727.
Company: CORELIS INC
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