It’s impossible to directly measure the stability (gain/phase) characteristics of a device if the device’s control loop lacks an access point to apply a test signal or can’t be broken. For many of today’s linear, switching and point-of-load regulators, the part is literally a closed system; even a hybrid regulator might not have an exposed control loop.
Fortunately, a new technique permits non-invasive stability testing of such devices.1 Designers can evaluate stability by measuring (on the bench) or simulating (on a computer) the device’s output impedance. The bandwidth and phase margin are calculated by analyzing the impedance’s group delay.
Group Delay And Stability
Group delay is the rate of change of phase with respect to frequency. It’s defined as:
In regulator analysis, the phase is the offset between two signals: the perturbated load current and the resulting voltage response of the regulator.
The group delay is easily calculated from the phase curve, using the post-processing programs in most Spice packages. A peak in the group delay marks a point of rapid phase change. There are two principal sources of rapid phase changes:
- A resonance, either from an LC filter, or the self-resonance of an inductor or capacitor
- The zero crossing point of a system’s loop gain
The high Q near zero bandwidth is a result of the gain curve coming very close to the singular unstable point at (1,0). The result is poor stability, which impacts all closed loop parameters, including PSRR, output impedance, reverse transfer, and the step load response. It can also result in increased output noise.
Each peak in the group delay represents either a passive resonance or low phase margin gain crossover. When the load current changes, the peaks can cause voltage oscillation at the resonance frequencies. High-Q peaks are more likely to provoke oscillation. Q is defined as:
where Tg is the group delay at a given peak, and Freq is the frequency of the peak.2 We can compute the phase margin from this Q.
Nyquist plots are used to evaluate closed-loop stability by plotting the gain-phase vector (in this case, of the output impedance) in Cartesian coordinates (with the real part of the impedance on the X-axis and the imaginary on the Y). It’s more useful to define the phase margin as the “stability margin,” as the margin is not always the phase offset from zero at the zero-gain crossing frequency.
The minimum distance between the plotted vector and (1,0) defines the system’s stability.2, 3 For example, a system where the gain and phase intersect at (1,0) is a perfect oscillator (Q approaches infinity). Phase margin (or stability margin) is, therefore, defined as:
The variations in a regulator’s output impedance can provide data to calculate the system’s phase margin, and by implication, its stability. Alternate methods, such as load stepping, do not provide a quantitative value for loop stability (though load stepping can provide a qualitative indicator of stability).
A quantifiable phase margin, a measurable number, is required when beginning-of-life (BOL) or end-of-life (EOL) performance requirements must be met. For example, worst-case analysis guidelines for aerospace applications generally specify a minimum of 30° of phase margin at EOL.
When using Spice (or any RF/analog simulation tool), a meaningful stability assessment must include component tolerances in the calculations. It is not sufficient to tolerance only the components external to the regulator IC; it too must be toleranced. These include tolerances for bandwidth, open-loop gain, and any component characteristics that interact with the load.
BOL phase margin testing does not preclude the need for EOL worst-case circuit analysis (WCCA), even if that testing is performed over the product’s specified temperature range. Experience shows that a degradation of 20° (or more) of phase margin is not uncommon, due to the tolerances associated with component aging. In addition, some regulators have an irregular phase response that worsens the BOL-to-EOL shift. WCCA is a necessity, not an option, if specifications need to be met over the life of the product.
Simulating Output Impedance
Simulating the dynamic output impedance of a regulator (in this case, the Linear Technology RH3080) requires adding an ac current source from the output to ground and perturbing the regulator’s static dc current output (Fig. 1).
Plotting the voltage of the regulator output, scaled to the ac magnitude of the current source, is equivalent to plotting its output impedance (Fig. 2, plot 2). To determine the regulator’s stability, we also need to plot the magnitude of the group delay (Fig. 2, plot 1).
There can be multiple peaks in the group delay plot. The peak we’re interested in is the one at or near the same frequency as a local maximum or minimum in the impedance.
Using the group delay and frequency of the peak, we can determine the bandwidth, Q, and phase margin. In this case, they are 20 kHz, 2.8, and 20°, respectively:
Measuring Output Impedance
Output impedance can be measured “on the bench.” It’s best done with production hardware and the actual loading the regulator will see, using the same measurements and procedures chosen for simulating the output impedance (Fig. 3).4 The required test equipment to make this measurement includes:
- A vector network analyzer that plots group delay (such as the OMICRON Lab Bode 100)
- A current injector (a device to perturb the output such as the Picotest J2111A)
- A 1:1 voltage probe
Following the connection diagram in Figure 4, connect the probe and the current injector to the regulator’s output. (The regulator’s ground is the reference for both connections.) The network analyzer’s signal modulates the current injector’s output. The transconductance of the J2111A, in particular, is 10 ms, so that a 1-V change in the modulation input results in a 10-mA change in the output.
The injector’s monitor output delivers a voltage proportional to the current flowing through the injector (1 A à 1 V). This signal is measured at channel 1 of the analyzer. The output voltage feeds channel 2 through the probe. The ratio (CH2/CH1) of the ac output voltage to the ac injected current is the output impedance which is plotted versus frequency:
The Bode 100 software calculates the Q and phase margin from the group delay, simply by positioning the cursor at the desired point on the plot (Fig. 5). The Bode 100 software is run on an external Windows based computer, connected via a USB port. The bench measurements and simulated measurements of the RH3080’s bandwidth and phase margin are in excellent agreement.
This methodology has been validated by testing parts that allow traditional Bode plots to be made. This measurement technique can be used to assess the stability of filters, linear regulators, switching regulators, op amps, and other circuitry. It permits real-world testing of both prototypes and production samples (Fig. 6 and Fig. 7).
For more information on using signal injectors to measure stability, please visit https://www.picotest.com/blog for articles discussing this and other topics.
- “New Technique for Non-Invasive Testing of Regulator Stability,” Steven Sandler and Charles Hymowitz, Power Electronics Technology, September 2011
- Erickson, Robert W. and Maksimovic, Dragan, Fundamentals of Power Electronics, Springer, 2004
- “When Bode Plots Fail Us”, Steve Sandler, Paul Ho, and Charles Hymowitz, AEi Systems, February 2012
- “Measurement of DC/DC Converters with Bode 100,” Omicron Lab