Electronic Design

Jitter-Tolerance BERT Targets Forwarded-, Embedded-Clock Designs

Testing of the physical layer in high-speed digital devices is becoming more challenging daily. The next generation of such devices will require forward-clocking architectures for memory-to-CPU interfaces, which will incur new signal-integrity (SI) and jitter problems. With data rates reaching 5 to 8 Gbits/s in serial-bus standards, designers will be thirsting for more sophisticated SI and jitter test capabilities.

Thus, in its J-BERT N4903 serial bit-error-rate tester (BERT), Agilent is zeroing in on validation and compliance test engineers looking to validate just these kinds of architectures (see the figure). “These designers live in the 8- to 10-GHz range,” says Michael Reser, sales and business development manager for Agilent’s Digital Test Division. The N4903 is suited for jitter-tolerance testing at speeds up to 12.5 Gbits/s.

As an example of the kinds of applications the instrument would be used for, Reser cites receiver testing for Intel’s Quick Path Interconnect (QPI) front-end bus, a forward-clocking scheme. In such clocking setups, the transmitter clock is sent to the receiver to enable proper sampling even when the transmit clock and data are jittered. The N4903 serial BERT meets the need to generate worst-case distortion on the clock and data signals and to analyze them properly for a bit-error rate.

In addition to QPI test, the N490B serial BERT targets PCI Express 2.0, USB 3, Hypertransport 3, and fully buffered DIMM 2 interfaces. Like the QPI scenario, all of these interfaces are forward-clocking types in which the clocks run at half the data rate. The instrument characterizes the jitter tolerance and margins of receivers for these buses by providing half-rate clocks with variable duty-cycle distortion to emulate the effects of non-ideal clocking. Users can inject jitter on the forwarded half-rate clock and on data signals with adjustable phase relations.

Thanks to built-in tunable clock-data recovery (CDR), the N4903 serial BERT delivers highly accurate total-jitter measurements. A white paper explaining the benefits of integrated CDR can be found at: www.home.agilent.com/upload/cmc_upload/All/article_CDR_MFR_tmt_072307.pdf

Pricing for the N4903B serial BERT with built-in tunable CDR starts at $139,000 for the 7-Gbits/s version and $179,000 for the 12.5-Gbits/s version. The instrument will be available for ordering in March, 2009.

Agilent Technologies
www.agilent.com

Video:
Michael Reser of Agilent Technologies demonstrates Agilent's N4903B serial J-BERT, which performs complete jitter-tolerance testing for forward-clocking and embedded-clock designs.

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