Electronic Design

Low-Noise Signal Generation And Fast Frequency Settling Time Can Coexist – Overcoming The Conflict

The performance requirements for signal generators have grown more demanding as the quality of receivers and the speed of test have increased. With increasingly congested spectrum as a driver, the industry develops new modulation techniques, components are advancing in speed and performance, and manufacturing volumes are increasing. Thus, the demands on cost-effective quality signal generation have never been higher.

This has created a fiercely competitive market in which signal-generator performance continues to improve while their prices fall, a familiar scenario in all aspects of technology from vehicles to mobile phones. Customers and consumers continue to expect more for less.

The test requirements found in RFIC design and manufacture call for signal sources with both low phase noise and high frequency switching speed, requirements that are invariably in conflict. As a result, performance optimization tends to target one requirement or the other but rarely both. A synthesizer design used in Aeroflex’s S-Series signal generators optimizes performance in both areas, with frequency switching speeds of less than 100 μs and typical phase noise at 1 GHz of -135 dBc/Hz at a 20-kHz offset.

Advances in technology have enabled the synthesizer design to be miniaturized and simplified so that it is a fraction of the size and cost of its predecessors. While enabling the signal generator to be light and compact, it also provides space for future expansion as the range of products expands. The following subsections of this article will look at aspects of the synthesizer’s design.

Multi-loop synthesizer

A multi-loop synthesizer design achieves a wide frequency range (up to 6 GHz) with fine frequency resolution. In this particular design, there are two phase-locked loops (PLLs). One provides a high-frequency, low-noise RF signal capable of stepping across the required range in coarse steps. A direct digital synthesizer (DDS) provides a low-frequency signal with a fine resolution to interpolate the coarse steps. These two signals combine in the second PLL to generate the final output signal.

Low-noise high frequency generation

Although surface acoustic-wave (SAW) oscillators have long promised low-noise generation of signals in the 1-GHz region, the best method continues to be by multiplication of a high-power VHF crystal oscillator. There is a conflict between starting with a high-frequency crystal for low noise, which will provide large and difficult-to-interpolate steps, and using a lower-frequency crystal, which provides smaller steps at the cost of increased noise multiplication. This conflict was resolved by using a 135-MHz crystal and a fractional multiplier, which provides a signal that covers 967 MHz to 1350 MHz in steps of 22.5 MHz. Starting from a 135-MHz crystal results in a noise floor some 16 dB better than would be obtained by using a 22.5-MHz crystal.

The designer of the crystal oscillator faces conflicting requirements. Good phase noise demands high-power operation and a narrow tuning range. The ability to lock the voltage-controlled crystal oscillator (VCXO) to a specific frequency over the life of the instrument in the face of crystal aging demands low-power operation and a relatively wide tuning range. The answer lies in running the oscillator at high power for low-noise performance, and then handling the crystal aging digitally. The 135-MHz crystal is phase-compared against the 10-MHz standard reference oscillator, which results in accurate frequency output. Dynamic programming of the interpolation synthesizer corrects deviation in real time.

Interpolation synthesizer

The interpolation synthesizer provides a tuning range of 11.25 MHz to interpolate the 22.5-MHz steps of the high-frequency signal. The output loop can subtract as well as add frequencies, so the required range is only half of the coarse step size. Other essential functions that the interpolation synthesizer is required to provide include:

  1. Fine 0.01-Hz synthesizer resolution when multiplied up to 6 GHz,
  2. offsetting the VCXO deviation from nominal frequency, and
  3. application of wideband FM.

A 720-MHz voltage-controlled SAW oscillator (VCSO) is phase-locked to the 10-MHz reference oscillator and used as the clock for a DDS. When the synthesizer is producing unmodulated CW, the DDS output has its already low spurious signals further reduced by a stage of addition to the 720-MHz signal, filtering and fractional division back down to low frequency. In this mode, it covers 22.5 MHz to 33.75 MHz. When the synthesizer is required to produce wide-deviation FM, the nominal interpolation frequency changes to the range of 33.75 MHz to 45 MHz, so that the interpolation signal can swing a further ±10 MHz to handle the wide frequency deviation. The DDS output is then used directly to cover the frequency range from 23.75 MHz (33.75 MHz - 10 MHz) to 55 MHz (45 MHz + 10 MHz).

Output addition loop

The output loop adds the two low-noise signals together. A fundamental low-noise voltage-controlled oscillator (VCO) covering a nominal range of 500 MHz to 667 MHz is doubled to 1000 MHz to 1333 MHz. This signal mixes with the low-noise, high-frequency signal. The difference frequency is then phase-compared against the interpolation signal. The phase detector output is low-pass filtered and fed back to control the VCO to complete the PLL.

An octave synthesizer would typically use a bank of VCOs to cover the output range, as achieving an octave tuning range with low noise is not straightforward. To achieve the required tuning range, a 1/3-octave VCO and is multiplied by 3, 4, or 5 to cover the octave.

This multiplier uses a lower-noise approach than previous designs. The 1000-MHz to 1333-MHz signal is doubled again to 4X the VCO frequency. This signal is used directly for the 4X output, or is mixed with the fundamental VCO to produce signals of 3X and 5X the VCO frequency. A tunable bandpass filter selects the upper or lower sideband. This use of doublers and mixers permits maintaining of a lower noise floor throughout the multiplication than would be the case with other methods.

Design for speed

To achieve a fully settled frequency transition within 100 µs while maintaining low noise introduces a further set of challenges. Analog voltages appear in several places in the synthesizer to pre-tune VCOs and to frequency-tune varactor bandpass filters. The tuning voltages have the conflicting requirements of being agile enough to move in microseconds, yet being quiet to sub-nanovolt level and free of drift once settled. We achieve this by using carefully selected low-noise DACs, switched-bandwidth passive filters, and filter capacitors with low dielectric absorption.

The PLLs in the fractional multiplier and the output addition loop use mixer-based phase detectors. While these have a very low noise floor, they have the disadvantage of a limited capture range, which is of the order of the PLL loop bandwidth. Conventional methods of acquiring lock, such as search oscillators, would be far too slow for this application. After a coarse pre-steer phase has steered the VCO frequency into the correct region, the VCO is accurately tuned before phase lock by using a digital discriminator technique (patent applied for). An FPGA compares the frequency of the two signals at the phase detector, and brings the VCO to the correct frequency by modifying the pre-steer voltage.

Once the VCOs are close enough to lock, they lock and settle very quickly, due to minimum PLL bandwidths of 200 kHz, achieving frequency settling to 0.1 ppm in 100 µs. This represents an error band of only 100 Hz at a 1-GHz carrier frequency.

Frequency modulation

The synthesizer is capable of producing wideband, wide-deviation frequency modulation, using standard two-point modulation. The FM system takes advantage of modern low cost digital processing to set the overall FM gain, and to match the gain and delay of the two internally calibrated paths. The modulation signal is applied simultaneously to the output VCO and to the interpolation synthesizer. As they vary together, the output PLL sees no error at the phase detector. AC and DC input coupling, as well as phase modulation, are also handled digitally.

Conclusion

The synthesizer achieves its design objectives through a combination of analog and digital techniques to provide excellent performance for the Aeroflex S-Series signal generators. This continues the evolution of generator technology that has been the hallmark of the Aeroflex product lines over several decades.

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