Verifying the amplitude of high-speed video pulses can be difficult. This circuit, a modified standard peak detector, measures the amplitude of RGB signals generated by a video RAMDAC (see the figure).
Examining the circuit, the input stage (U1)—a high-speed buffer—isolates the measurement circuit from the video-signal generator. When doing measurements, a high-speed comparator stage (U2) compares the video signal's amplitude to the voltage on the hold capacitor (C1). If the video signal has a higher amplitude, the comparator generates a high output. This causes C1 to charge to a higher voltage. When C1's voltage equals the maximum amplitude of the video pulses, the comparator stops providing a charge signal.
Transistor Q2 provides the charging current for C1. Q2 remains on to minimize the charging voltage's propagation delay and rise time. Diode CR1 isolates the hold capacitor from the output of Q1; it conducts only when Q1's output is high. The diode must be capable of high-speed switching and have low leakage current in the off state. Output stage U3 buffers the hold capacitor from the output load. It must have a slew rate at least as fast as the charging rate of the hold capacitor. Moreover, because of hold-time considerations, U3 must have low input bias current.
Measurement time depends on the application of the Hold and Reset signals. The time can be as short as one horizontal scan or as long as a complete video frame.
To reset the circuit, the hold signal must first be applied, followed by the reset signal. The comparator has a latch function that maintains the last comparator output state. The reset signal enables the latch function, thus assuring that the comparator's output is low during the reset state.
During the hold state, the input signal doesn't reach the comparator, making C1's charge independent of input signal. Measurement accuracy depends on how much the charge changes during the hold state. Different elements affect accuracy, such as the input bias current of U3, and the leakage current of CR1, CR2, and C1. Q1, enabled by the hold signal, provides the hold function.
The reset state involves enabling the hold function and discharging the hold capacitor. Turned on by the reset signal, Q3 supplies the discharge action. CR2 isolates Q3's leakage current from the hold capacitor, providing some compensation for CR1's leakage. The circuit composed of CR3, C2, and R2 provides a reference voltage of about-0.7 V for C1, Q1, and Q3.
The amplitude detector produces a dc output voltage equal to the input signal's maximum amplitude. Theoretically, the output voltage's resolution depends only on the comparator's offset voltage. In practice, there are other application-specific considerations; i.e., the signal amplitude at the comparator's input must be 1 V or less.