Electronic Design

P1500: The Standard For Embedded Test

In current system-on-a-chip (SoC) development, no standard access mechanism exists for testing embedded logic cores. Each core provider develops its own process for isolating the core and testing it. These methods are sometimes in conflict, making it difficult to use cores from multiple vendors in the same SoC design. As designers have still generated and applied tests for SoCs, clearly this isn't an insurmountable problem. Even so, the process could be smoother.

To improve the situation, the IEEE P1500 Standard for Embedded Core Test (SECT) working group was established. This team's goal is to provide an independent, openly defined, DFT method for the "automatic identification and configuration of testability features in integrated circuits containing embedded cores." These features will offer a standard method for routing test data and commands from external pins on the device to any selected core within the SoC.

The proposed standard is associated with CTL or "Core Test Language." CTL (IEEE P1450.6) describes the control of the core wrapper and the methods to be employed in testing the core itself. When completed, automatic creation of both the core isolation and core test will be possible. This will reduce the amount of time dedicated to test preparation and will facilitate core reuse.

P1500 will "wrap" a core with an electronic "blanket" that isolates through the use of isolation registers and tests the core. Core test may occur using the serial access to the wrapper for scan-based testing, or through a user-defined Test Access Mechanism (TAM). The chip designer determines the TAM's structure and may accommodate such things as parallel testing of a core or BIST. The P1500 access and control mechanism and the test wrappers may be serially linked together for test and control from a single small set of pins on the device.

In this way, a single serial scan chain can wind its way through every core wrapper, simplifying test control. The mechanism chosen for managing this serial link is the IEEE 1149.1-defined Test Access Port (TAP). P1500 recognizes the need for the TAM without constraining it unnecessarily. This is the power of the P1500 proposal: accommodation of unique test methodologies along with standardization of test control and core isolation.

P1500 is still a work in progress. The P1500 working group first met in October 1995 and began its effort in earnest one year later. Today, it's putting the finishing touches on the standard, currently expected to go to ballot next February. For more about IEEE P1500, visit http://grouper.ieee.org/groups/1500/. For more information on CTL, go to http://grouper.ieee.org/groups/ctl/.

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