With equipment providers looking to introduce new communications technology at much lower costs of procurement and operation, faster interfaces are becoming more important. As a result, serializer/deserializer (SERDES) circuits have become the most critical macrocells being tested. One of the toughest challenges customers face is integrating SERDES into new application-specific ICs (ASICs). A SERDES receives a fast serial signal (e.g., 2.5 Gbits/s) and deserializes it into slower parallel signals (e.g., eight 311-Mbit/s signals). With data rates increasing, many companies want to integrate a SERDES into their ASICs and other large digital chips. Problems arise because IC suppliers aren't fully testing the SERDES before integrating it into a design. For ASIC customers, reducing costs requires the IC supplier to understand signal integrity issues, pre-test important intellectual property (IP), and provide testability features in the macros.
With the sharp, prolonged downturn in the communications industry, companies have shifted their focus from pursuing cutting-edge technology that builds network capacity to providing highly competitive offerings enabling new services at a much lower cost. Companies must leverage comprehensive communications IP portfolios and improve signal integrity. With the higher data rates, SERDES macrocell integration is one of today's most important issues. Integrating SERDES functions into larger, system-level ICs lowers system cost compared to standalone SERDES devices. Integration also cuts power consumption and improves signal integrity.
To win, companies must successfully integrate SERDES the first time, and pre-testing ensures that. Customers are demanding to see test silicon before integration and are increasingly sharing their frustration that SERDES providers are not enabling first-pass success. Keeping costs low begins with with first-pass success. It ends with ramping to production volume quickly.
CO-DESIGNING RESOLVES ISSUES
Maintaining signal integrity is critical in designing a SERDES for integration, especially at data rates of 3.125 Gbits/s and higher. Instead of starting with the design and worrying about the package later, the macrocell, I/O buffers, and package substrate should be co-designed, so issues in each area can be discussed from the start and "negotiated" between die and substrate. For example, a layout that offers the smallest die may cause the routing of the complementary signal lines of a differential pair on the substrate to have different lengths, which hurts signal integrity. Co-design addresses these tradeoffs early in the process. Even though each ASIC will likely require a new substrate design, co-design will provide the optimal IC and substrate guidelines for good signal integrity.
Testing should be addressed early, ensuring that the SERDES will include features such as built-in self-test for critical blocks, phase-lock-loop bypass circuitry, and pseudorandom-bit-stream generators and checkers. A good design-for-manufacturing strategy includes low-cost ways to test the device in production, as well as during design verification and characterization.
Well before production, a test chip should be built, verified, and characterized. By evaluating the SERDES in a test chip, designers reduce the likelihood of finding problems in the integrated ASIC. If problems are found, they can be more easily studied in a test vehicle than in a large, complicated digital device. This pre-testing of IP via a test chip accelerates evaluation of the integrated device and reduces the probability of having to re-design it and pay for new masks, which are expensive for 130- and 90-nm processes.
Delivering a high-speed interface isn't enough. As interface speeds increase to 5 to 10 Gbits/s, all the issues will be exaggerated. Having a method of co-design, integration, pre-integration testing, and production testing in place will help macro suppliers and their customers achieve high performance with faster time-to-market and lower cost.