Electronic Design

Probing Problems With DDR SDRAM

Coming soon to a PC near you is double-data-rate (DDR) SDRAM. This low-cost, high-performance technology targets both PC memory buses and embedded designs like high-end graphics systems. So how do you learn about this new technology and, more importantly to designers, how do you debug a PC system that uses DDR SDRAM?

A company called Education News & Entertainment Network, El Monte, Calif., is offering a compelling educational and informational tool about DDR SDRAM for free. This company sponsors the NetSeminar series and its Internet seminar on DDR, entitled, "The Challenge of DDR PC266 and Beyond: Design and Validation of High-Speed Memory Buses." Perry Keller, senior engineer program manager at Agilent Technologies Inc., and Greg Buzard, marketing engineer for FuturePlus Systems Corp., make the presentation.

Both Keller and Buzard mix the technical presentation with references to their own products—logic and bus analyzers. But overall, the presenters do a good job reviewing DDR SDRAM buses and providing insight into the various nuances of the signals on the bus. For example, one slide shows how the read and write signals of DDR burst timing differ (see the figure). The presentation also delves into such issues as the tools that you will need to perform DDR validation, as well as finding and maintaining the data eye. Another slide provides a direct comparison between PC133 and DDR buses.

The seminar was originally presented on December 12, 2000. But you can catch a rerun at any time, because all ENEN seminars are archived at the ENEN Web site: www.netseminar.com.

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