The circuit shown in Figure 1 provides a simple, low-power means of digitizing analog signals and sending the data directly to a PC's serial port where it can easily be read, analyzed, and stored. The low power requirements of this circuit allow it to be powered directly from the control signal outputs of the serial port. Thus, no external power supply is required.
When power is applied, the circuit continually samples the analog input at the frequency set by the sample clock. It transmits the data serially to the PC at the baud rate set by the baud-rate clock. Sampling frequencies up to 4 kHz can be achieved by the circuit as shown. These sampling rates make this circuit suitable for chart-recorder-type applications.
The circuit is comprised of an 8-bit parallel analog-to-digital converter (ADC) with an internal sample-and-hold and voltage reference (U1), a sample-frequency oscillator (U2), a baud-rate oscillator (U3), gating circuitry (U4 and U5), parallel-in/serial-out shift registers (U6 and U7), and power-conditioning circuitry (VR1 and nearby components).
The ADC's parallel outputs are connected to the shift registers such that they can be shifted out in order from LSB to MSB following the hard-wired high start bit at U7 pin 14. The stop bit and all trailing bits are hard-wired low (U6 pins 13, 4, 5, 6, 7, and 11, respectively) to complete the formatted serial byte with 8 data bits, no parity, and one stop bit. The serial output from this circuit at U7 pin 3 is a 0- to 5-V signal, which is adequate to be recognized as having pseudo-RS-232 logic levels by most PCs. The ASCII value of the eight data bits is inverted due to the RS-232 convention of a logic zero being a high-level voltage. This inversion can easily be corrected in the software used to read the data from the serial port.
U1 is the MAX165 CMOS-microprocessor-compatible, 5-µs, 8-bit, parallel-output ADC. The analog input voltage range is 0.0 to +2.46 V. U1 is configured to use its internal conversion oscillator with the 100-kΩ resistor and the 100-pF capacitor connected to pin 5. With this setup, the typical conversion time is 5 µs. An A/D conversion begins on the falling edge of the sample clock, which is connected to the —RD input of U1. The —BUSY signal of U1 is low during the conversion and transitions high to indicate that the conversion is complete. Data from the most recent conversion is available at the parallel outputs within 80 ns after —BUSY transitions high.
The rising edge of —BUSY clocks the D flip-flop, U4B, to produce a falling edge on the -Q output that latches the parallel data into the shift registers. The delay through U4B allows the ADC's parallel outputs to set up prior to being latched into the shift registers. Then, U4B is reset by the high level of the sample clock. The baud-rate oscillator output is gated by U4B's -Q signal, and data begins shifting out of the registers on the falling edge following the first rising edge of the baud clock after a conversion is complete. This gating is required to ensure that no partial baud-rate clock periods appear at the beginning of the data stream.
The circuit as shown runs at a baud rate of 115.2 kbits/s, which is set by the 86.6-kΩ resistor between U3-1 and U3-3. The accuracy and stability of U3 is such that no trimming is necessary to obtain adequate baud-rate timing. The sampling frequency is less critical and is therefore set by a CMOS 555 timer to minimize power consumption.
The circuit was tested with sampling rates from 100 Hz to 4 kHz. The total 5-V supply current for this circuit was measured at about 4 mA, which is easily provided by the DTR and RTS modem-control signal outputs of the PC's port. The supply voltage for all of the ICs is regulated by the 5.1-V Zener diode, VR1.
On the PC end, many software implementations are possible. Home-grown C code or applications such as LabView can easily be used to perform the following steps to set up and receive data: (1) Set up the desired serial port (such as COM1) for the circuit's baud rate (115.2 kbits/s for the circuit shown), eight data bits, no parity, and one stop bit. (2) Set the DTR and RTS modem-control outputs high to apply power to the circuit. (3) Begin reading received data from the serial port buffer. The ASCII value of each character read from the buffer must be subtracted from 255 to account for the data bit inversion discussed earlier. The software can then become as elaborate as the application requires. This can range from simple data logging to a full-blown virtual oscilloscope with triggering, display, histogram analysis, etc.
The serial port buffer can be read at a convenient, noncritical timing interval set by the software. This interval can be up to several seconds, depending on the size of the receive buffer and the sampling frequency of the circuit. Regardless of the interval chosen, the appended data points will maintain the point-to-point time spacing set by the sampling clock of the circuit.
This circuit can be used to monitor low-frequency transducers such as seismic or pressure sensors. Additional analog signal-conditioning circuits (gain, scaling and filter networks) can be added to this circuit without the need for an external power supply. A plethora of micropower, single-supply voltage operational amplifiers are commercially available to perform such functions.