Electronic Design

Short-Pulse Stressing Outdoes DC Testing For Advanced Semiconductors

Developing ICs that work is one thing. Developing them to last is another. And that’s getting more difficult as new technologies and devices present new reliability problems. Pulse testing on-wafer, before packaging, can help.

The problem is that traditional dc testing of advanced IC technologies may not uncover reliability problems caused or exacerbated by new materials and devices. Shrinking geometries, new materials, and more complex designs are greatly reducing device lifetimes by increasing fragility, raising power density, and introducing new failure mechanisms. This is especially true for nanoscale gate dielectrics using new high-K materials. Processes that once produced devices with 100-year lifetimes may now yield only 10-year lifetimes or less—uncomfortably close to expected system lifetimes. Therefore, reliability must be designed in from the start, tested thoroughly, and constantly monitored in production.

Today, accelerated reliability tests such as hot-carrier injection (HCI), negative-bias temperature instability (NBTI), and time-dependent dielectric breakdown (TDDB) are used to quickly generate curves that can be extrapolated to predict operating lifetime and provide insight into device design and manufacturing processes. The most efficient method is to overstress the device, measure degradation trends of key operating parameters, and extrapolate the data to the expected lifetime at actual operating conditions.

But due to the new materials, smaller geometries, and nontraditional device structures, reliability testing may need to expand beyond current implementations. For example, today’s repetitive dc stress cycling with test setups that use a switch matrix can allow unplanned or unmeasurable relaxation of degradation effects. In the actual operating environment, there may be no time for device relaxation. Therefore, traditional dc stress testing may significantly overestimate lifetime and operating performance.

On the other hand, dc tests may cause other kinds of degradation not seen in the operating conditions that may significantly underestimate lifetime and performance. For instance, a device under dc stress may show self-heating effects that are more severe than a device actually being clocked at high speeds or only turned on periodically. Or, a device being switched on and off at a high rate of speed may never get the chance to degrade due to charge trapping as a dc test would imply.

The answer is to characterize and test these devices in a more realistic manner than traditional dc stressing through the use of ultra-short but flexible pulse testing. For example, degradation of threshold voltage can be measured as a function of pulse frequency, separated from the artifacts caused by dc stress. This provides important information about the nature of degradation and recovery in different operating regimes, and it can even depict the intrinsic operation of the device (i.e., without charge trapping or isothermal effects). Understanding the full effects of materials, process, or design changes on device performance and reliability in a wide variety of potential operating conditions is vital to the technology development and circuit design process.

Use of the pulse technique is particularly important in qualifying high-K gate materials and production processes for leading-edge CMOS technologies. While the material and process is maturing, many interface states and traps are in the material. To characterize them fully, multiple measurement techniques are typically required, including dc I-V, pulse I-V, C-V, and charge-pumping measurements.

A new technique, single-pulse charge trapping (SPCT), uses a pulse generator to do fast I-V curves to either avoid charge trapping or to measure charge trapping as a function of a device’s switching frequency. The key to success in SPCT is to make measurements in a controlled but variable time domain. With pulse rise and fall times ranging from a few nanoseconds to milliseconds, you can model different switching speeds and determine charge trapping behavior at different operating conditions.

The core instrumentation requirement for SPCT and other pulse I-V testing is a semiconductor characterization system with sub-femtoamp resolution (for gate leakage-current measurements), an integrated ultra-short pulse generator, and measurement bandwidth high enough to capture device responses down to tens of nanoseconds—and, of course, the control software to make it all work.

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