Electronic Design

Simplify SoC Development With Embedded Testing

While the use of complex system-on-a-chip (SoC) designs has increased, unfortunately, that hasn't increased the time-to-market window for designers and chip manufacturers. As SoC designs become more complex, the development time remains about the same—from nine to 12 months—whether the SoC device being designed contains 1 million gates or upwards of 10 million gates.

To increase time-to-market windows, hierarchical design methodologies have to be employed. ICs are simply becoming far too complex to leave the testing function until after an SoC has been designed, packaged, and readied for testing.

A current-generation 10 million-gate SoC device can contain more than 200 embedded memory blocks, predesigned third-party intellectual-property (IP) cores, blocks of logic, a block or two of phase-locked loops (PLLs), and some data converters. Such complexity can't be handled with conventional design methodologies. Rather, it requires a hierarchical approach to design.

Testing these complex SoC devices also is an increasingly important part of the time-to-market equation. How can you test all of these blocks without the forethought of a structural test strategy?

The sad truth is that you can't. Moreover, the need to make testing less expensive as the cost of automatic-test-equipment (ATE) systems rapidly increases is another significant factor in this equation.

To meet these testing challenges, the use of an embedded test strategy is becoming a necessity and will soon be inevitable. Hierarchical design and hierarchical testing must go hand in hand.

With the use of hierarchical embedded testing, it's possible to reduce the total test development and debugging time by as much as 70%. This has significant implications on the time-to-market window. Both test development and debugging processes are lengthy phases for design and test engineering teams. Test development and debugging are two aspects that often take weeks to months.

Devices designed hierarchically lend themselves to a simpler timing closure with fewer iterations. Such an approach divides a design into several smaller blocks, performing physical layout and reaching functional timing closure on each individual block, and subsequently completing the design by stitching the blocks together at the top level.

Embedded testing enables the design team to insert a test infrastructure into each block, linking this activity with the basic hierarchical design. Design functionality and embedded testing can also be combined in the same way as reusable cores. IP with integrated embedded testing offers plug-and-play readiness for both functional and structural testing. This has enormous implications for manufacturing. For example, imagine a 10 million-gate SoC designed for a cell phone. Such a chip almost certainly won't sell for $100; market demands will more likely dictate that it be sold for $10.

The total cost of manufacturing such a chip will be around $6, with the cost to test it using traditional external testing methods at about $1. Test functions traditionally handled by these external testers, such as cores, pattern memory, timing generators, and algorithmic pattern generators for memories, can all be implemented on-chip through embedded testing. Using this approach can reduce testing cost by at least 50%. This has a major effect on SoC devices shipped in large volumes of, say, 10 million units or more.

Embedded testing achieves additional value by providing on-chip test functions that are incredibly expensive to obtain from an external ATE system. Although some functions still require the use of an external tester, the digital functions can be completely addressed by providing embedded testing on the chip. This allows chip makers to leave more complex analog functions, like RF, power, and analog-to-digital and digital-to-analog conversion, to ATE systems that are optimized for testing specific analog functions.

By combining test solutions for an on-chip and off-chip test strategy, an optimized solution can be realized, including at-speed testing of logic. Because embedded testing is designed into the chip with the same architecture, the ability to test the chip at-speed is inherent. In fact, testing at-speed, or at multiple speeds, can be performed without the need for complicated and expensive ATE systems, add-ons, or changes.

Using embedded testing as a strategy from design through manufacturing can simplify SoC development through its hierarchical implementation. Embedded testing can reduce external test costs by 50% and total test development and debug time by 70%. It also positively impacts the time-to-market window, while ensuring superior quality SoC designs and reduced testing costs.

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