Electronic Design

Software Lets SoC Tester Use EDA Design, Simulation Files

The SmarTest PG software for the Agilent 93000 system-on-a-chip (SoC) test system makes the tester "design ready" so it can accept EDA-generated design and simulation files. The software replaces the complex array of scripts and tools normally used to translate EDA output to a tester-ready program.

SmarTest PG generates directly loadable 93000 program files with output features like pattern generation, timing and ac specifications, pin configuration, and dc levels. Additional capabilities include graphical timing capture, simulation and ouput analysis, complex and midcycle I/O support, equation-based timing throughput, and incremental program generation.

SmarTest incorporates foundation technology from Test Insight Ltd., Israel, an Agilent partner in design-for-test tools. Test Insight's technology supports multiple clock domains, enabling SmarTest to take advantage of the concurrent test capability within the 93000.

Users can intuitively map their complex design simulations into the 93000's per-pin timing architecture. Device cycle timing is captured and implemented in a test that exercises the full range of the device's behavior. The software's graphical editor gives users full control to manipulate and analyze simulation waveforms in real time throughout the conversion process.

Pricing for SmarTest PG for the 93000 SoC Series Test System starts at $24,200 for a one-year floating license, including support. The flexible pricing structure also includes alternatives for one-month and perpetual floating licenses.

Agilent Technologies Inc., www.agilent.com/see/smartestpg.

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