Electronic Design

Test-Compression Technology Makes The Most Of Semiconductor Testers

Testing can represent as much as half the cost of semiconductor device manufacture. To reduce that, Mentor Graphics' TestKompress uses a new compression technology that lets designers cut the amount of ATE memory and time needed to test ASICs, ICs, and systems-on-a-chip (SoCs) by a factor of 10. This reduction permits maximum usage of existing test equipment while also cutting the cost of future testers.

The technology is called Embedded Deterministic Test. Test data compression results from a combination of embedded test logic and new deterministic test-pattern-generation algorithms. The test logic is embedded at the interface between the scan chains and the tester pins without any changes in the system logic. Also, the tight coupling of test logic and test-pattern generation eliminates the need for test-point insertions and the "X" bounding logic used in other design-for-test (DFT) methods.

TestKompress is fully compatible with scan and automatic test-pattern-generation (ATPG) DFT flows. It uses the same scan DFT methods, script files, and ATPG libraries as Mentor's Fast-Scan, and it supports all scan methodologies and fault models. TestKompress uses the same test vector formats and tester interfaces, so ATE integration and adoption is seamless.

TestKompress comes in two versions. TestKompress 5X reduces test data and time by up to five times. TestKompress 10X offers benefits of up to 10 times. Available immediately under term licenses, prices start around $2 million.

Mentor Graphics Corp., (503) 685-7000; www.mentor.com/dft.

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