With clock rates in the latest CPUs zooming past the 1-GHz barrier and with the onset of Gigabit Ethernet, a major revision of the Peripheral Component Interconnect (PCI) bus specification was clearly needed. Last September, the PCI specification was upgraded to the PCI-X specification. The PCI-X bus architecture calls for significantly higher performance than the earlier PCI version. PCI-X is expected to meet near- and long-term demands for performance scalability because it calls for data throughputs up to 1.066 Gbits/s—an improvement of eight times over the conventional 32-bit, 33-MHz PCI bus. PCI-X stipulates 64-bit as well as 32-bit systems and adapter designs that can operate over the 66- to 133-MHz range. As a result, the new architecture requires advanced design and development test tools.
To meet such requirements, Agilent Technologies has introduced the E2929A PCI-X exerciser/analyzer and the E2922A PCI-X master target test card. This set of tools is intended to validate and debug chip sets, servers, server clusters, RAID systems, and interface cards, as well as other designs using the bus PCI-X interface.
Although the two tools have a number of features in common, they're targeted at different users. The E2929A is aimed more at the design and debug phases (Fig. 1). The E2922A, on the other hand, is configured so that multiples of this test card can be plugged into card slots to behave as exercisers, thereby performing validation and stress tests.
A design verification and diagnostic tool, the E2929A exerciser and analyzer enables fast and predictable debug, optimization, and validation of various PCI-X-based designs (Fig. 2). Suitable environments might be where one wants to connect an external controller to the card, such as a desktop PC running Windows. Configured as a short PCI-X card, the E2929A is simply plugged into the system under test. It can be controlled by an interactive graphical user interface (GUI), or with the addition of an option from a specific customer C program using an open C application programming interface (C-API).
A protocol checker, which is standard in the E2929A, is designed to verify that a design complies with the PCI-X protocol. The checker runs continuously, alerting the designer to PCI-X protocol rule violations in real time. All of the 50 protocol rules, which are derived from the PCI-X specification, are checked concurrently. Any rule can be individually masked to suppress the triggering of known problems.
The E2929A reports errors that occur. Plus, the checker can trigger the optional plug-on PCI state analyzer's trace memory. It also can trigger a FuturePlus PCI-X analysis probe.
The plug-on PCI-X state analyzer with 2 Mbytes of trace memory offers significant trigger and storage qualifier capabilities. This makes it relatively easy to identify complex error conditions. In addition to conventional pattern terms for all PCI-X signals, a bus observer makes the current bus status—address phase, attribute phase, data phase, idle phase, and so on—transparent. As a result, it simplifies the setup of trigger conditions. By combining additional error pattern terms, external trigger inputs, and trigger sequencer capabilities, the E2929A can capture necessary data.
The E2929A PCI-X state analyzer observes all signals, except JTAG, in accordance with the PCI-X specification for a 64-bit 66/100/133-MHz system. It captures 64-bit PCI-X address/data/control signals, PCI-X protocol errors, bus observer signals to decoded bus state signals time-aligned to the bus signals, and active master and target signals aligned with the bus signals, for easy identification of transactions involving the exerciser. Furthermore, it captures four signals from the trigger I/O connector.
Through the use of pushbuttons, the state analyzer storage qualifiers can be programmed, depending on the level of detail necessary, to store all states, to store only particular bus transactions by command type, to suppress idle cycles, or to suppress wait cycles. The plug-on PCI-X state analyzer comes with a Windows-based GUI.
For efficient system debugging and software development, the FuturePlus PCI-X analysis probe is the optimal solution whenever X-correlation becomes essential between the PCI-X bus and other system interfaces. For instance, suppose one has to set up a server and wants to figure out what went wrong in the system. This person would want to see what's happening on the CPU bus, as well as on the PCI-X bus.
One would use the PCI-X protocol checker, plugging in the FS2104 FuturePlus logic analyzer link card (available through Agilent as resale part FSI-60042). State analysis could then be performed on the logic analyzer for both the CPU bus and the PCI-X bus.
With the FuturePlus PCI-X Analysis Probe, therefore, the E2929A PCI-X protocol checker becomes an integrated part of the 16700 logic-analyzer system. Additionally, FuturePlus offers a passive probe known as the FS2101. It allows both state and timing analysis with the Agilent 16700 logic-analyzer system.
By simply plugging the Analysis Probe into the E2929A, each PCI-X signal is clocked into the Agilent 16700 logic-analyzer system, together with a protocol-error signal. When the probe is attached, all PCI-X and protocol-error detection signals are clocked through to the logic-analysis system where they are inversely assembled into PCI-X mnemonics.
A fourth E2929A option is a PCI-X exerciser. It can be controlled through a GUI, the command line interface (CLI), or the optional C-API. The CLI runs under Windows 98/2000/NT. This allows the user to interactively control the PCI exerciser and analyzer from an external PC by entering command functions that correspond with the functions provided by the C-API. The CLI can process batch files of concatenated command functions.
The exerciser operates over the 0- to 133.4-MHz range and can emulate and force practically any imaginable behavior from a PCI-X device, except blatant protocol violations. The exerciser comes with a GUI and a CLI. As an option, the exerciser can be controlled from a C-API.
The GUI affords an easy way to set up and control the exerciser in a table-type format with selection boxes, so the user doesn't have to remember obscure syntax. It provides a convenient way to force dedicated test cases by stimulating the required PCI-X traffic. The exerciser supports two requester initiator streams and a completer initiator to fully support split transactions and multiple-traffic streams.
The optional C-API provides a programming interface for setting up and controlling the exerciser and analyzer. This option comes with a PCI Protocol Permutation and Randomizing (PPR) library.
The test program can either run on the actual system under test, or else on an external controller. If the program runs on an external host, the E2929A connects to the external host via an RS-232 or fast parallel port. On the other hand, if the test program runs on the system under test, then the PCI-X interface itself is used. Drivers are provided for each interface, which allow the C-API to be implemented with Windows NT/95/98/2000. For Linux, HP-UX, and proprietary operating systems, a porting support service is available.
The E2929A has several options available. Option 100, which includes a PCI-X plug-on state analyzer, makes it possible to utilize the PCI-X state analyzer's capabilities from a logic analyzer. It can also be controlled from a GUI. (Option 100 doesn't enable the link to the 16700 and requires a separate option.) Op-tion 100 transforms the E2929A into a standalone state analyzer.
Option 300, which adds exercising capabilities, includes 32/64-bit, 0- to 133.4-MHz exerciser hardware, a GUI for Windows, and a software media CD. Option 320, which can be added as an augmentation to option 300, enables PPR in hardware and a C-API interface for one test card, plus drivers for Windows NT/2000.
The E2922A master target test card offers a selection of the E2929A features (Fig. 3). It's intended for validation labs where multiple PCI-X masters and targets are needed for validation of high-end systems and chip sets. The E2922A is well-suited for test setups where a full population of test cards in the available PCI-X slots is required.
Because the E2922A features a fully controllable master and target (PCI-X exerciser), a real-time data compare, and a protocol PPR technique, it enables engineers to validate and stress a PCI-X system with specific and fully repeatable test cases. For test engineers in the semiconductor industry, then, the E2922A offers a fast and predictable way to setup PCI-X traffic and verify the PCI-X protocol compliance of first silicon.
System benefits include fully programmable traffic behavior, easy integration into existing test frames, and predictable setup of transactional and data-level test for PCI-X-based silicon. Furthermore, the test card stresses corner cases predictably and repeatedly, handling over 1 million test cases in less than 5 seconds.
Like the E2929A, the E2922A is configured as a short PCI-X card that can be easily plugged into the system under test. It includes the checker and exerciser described above. Plus, it comes with a C-API that provides a programming interface for setting up and controlling the master target card.
Also included is a PPR library that extends the C-API by offering dedicated functions to set up a PCI-X protocol in a pseudorandom sequence. It additionally enables the user to set up transfers of contiguous blocks of data with as many protocol variations as possible. The E2922A doesn't provide a standalone state analyzer, GUI control, or control from an external host. The FuturePlus card can be connected in order to interface to the 16700.
The test program must run on the system under test itself. The PCI-X interface is used to control the card. Drivers are provided for each interface that enables the C-API to be used with Windows NT/98/2000. For Linux, HP-UX, and proprietary operating systems, an optional porting support service is available.
The E2922A is compatible with the E2929A. Programs developed for the E2922A, therefore, can be executed using the E2929A. Also, the two cards can be operated within one system.
When the objective is to populate large systems with lots of these cards, designers would want control to be derived from a programmed environment. The test program must run on the system under test itself.
The optional E2977A design verification test library offers ready-to-use stress tests that can be fully integrated into existing test frames.
The E2922A includes a connector for connecting to a logic analyzer through a FuturePlus probe. Thus, all PCI-X related signals can be easily acquired using the Logic Analyzer. The connector is compatible with the FuturePlus 2104 logic-analyzer link.
Price & Availability
Available now, the price of the E2922A PCI-X master test card, including protocol checker, exerciser, PPR, and C-API, is $11,500 in single-unit quantities. The companion E2977A design verification test library is priced at approximately $18,000. It will be available in November.
The price of the E2929A base product, including the 32/64-bit, 0- to 133.4-MHz PCI-X protocol checker, RS-232 and USB cables, protocol checker, graphical interface for Windows NT, and software CD, is $4900.
Option 100 and Option 320 are priced at $5200. Option 300 is priced at $5300.
Agilent Technologies, Test and Measurement Organization, 5301 Stevens Creek Blvd., MS 54LAK, Santa Clara, CA 95052; (800) 452-4844, ext. 6910; www.agilent.com/find/pci_overview.