Waking up to a specifications nightmare

Here's the scenario: Engineering just designed a high-speed serial interface for your flagship product. The VP of engineering drops the prototype on your desk and says, "Make sure this design meets the serial-interface spec. If there are any compliance issues, I want to know now before we go into production. And while you're at it, find some way to qualify the incoming ICs we'll use to implement that serial bus." You pull out a copy of the spec and just stare at the pages: How do you know which sections pertain to your product? How do you interpret the requirements, and what exactly must you test? Even then, would you know how to set up and run the tests to verify the required parameters? Do you have the necessary test gear?

Many of you likely know what a nightmare situation this is. You also know that plowing through those documents for hours on end is only the start; getting an adequate test setup takes many more frustrating hours. Be forewarned, though-the need to design to high-speed serial interface specs will become ever more important to ensure interoperability. As these speeds reach 6 Gbps and beyond, you not only need the latest high-speed scopes but also exact testing techniques and test fixtures. In the past you could build most parallel bus schemes somewhat loosely with regards to standards. But now, with serial bus schemes you must follow strict rules regarding what a signal should look like. Further, interoperability problems have plagued some past and present schemes, so standards organizations are imposing strict requirements on firms that wish to market "logo" products, and they're being aggressive about enforcing compliance.

Let's consider a real example: PCI Express. This 3rd-generation I/O interconnect specifies rates of 2.5 Gbps with an edge rate <100 psec. PCs and peripherals using this scheme are already coming to market. Want to join them? The PCI-SIG web site (www.pcisig.org) discusses two things required to get a product on their Integrator's List and use the PCI Express logo: Submit a compliance checklist that involves subjecting a product to intricate tests, and then take part in a compliance test, also known as a plugfest.

Recognizing how tough it is for design engineers to fulfill these requirements, the PCI-SIG has taken a leading role in supplying information to help engineers better understand exactly what the spec demands and how to perform the tests. For instance, SIG members have access to the PCI Express Electrical Testing tools, which consist of documentation that outlines recommended procedures, test software (known as SigTest), and even test fixtures for both platforms and add-in cards.

Knowing what to test for is one thing; actually conducting the tests is another. The difficulty often involves setting up specific instruments, calibrating probes and then analyzing detailed results. Another factor that leaves considerable work for test engineers is that SigTest provides minimal reporting capability. Instrument vendors have spotted a market niche here-thank goodness. They've taken the PCI-SIG requirements and even the SIG's own clock-recovery software and tightly integrated them with their instruments to create 1-button automation of all the tests required for full compliance and margin testing. Further, the software provides a test-setup walkthrough for each specification assertion to ensure proper electrical termination and connection to the DUT. Their software automatically configures the instrument for each test, and the resulting report includes not just pass/fail info but also margin analysis indicating how close the device is to passing or failing a particular test assertion. Further, when you discover a problem, debug tools can aid in root-cause analysis.

Arriving at something of this sophistication was hardly easy, even for experts. Specialists from leading instrument companies spent considerable time in working groups looking at the test assertions, getting agreement on what they meant, working up a test procedure and troubleshooting it. "Participation in working groups and SIG-sponsored workshops is key to knowing how to make the measurements called out in the PCI Express specification," says Rick Eads, Serial Applications Program Manager at Agilent. "Still, figuring out how to implement the right tests to make the measurements called out in the spec was not trivial. Our hope is that our tools can streamline some of that process."

However you approach this problem, don't forget that emerging communications standards bring with them new testing requirements. Further, test houses can go a long way beyond simply providing instrument hardware in helping slash the time you need to ensure product compliance.

For more information on high-speed serial specifications and validation testing, go to www.agilent.com/find/curveOl-nov04