Memory Request Optimizer (MRO) from Performance-IP helps improve memory efficiency and increases the performance of a SoC by reducing memory latency between the memory subsystem and the SoC client. Programmable memory optimization offers in-system analysis to dynamically reconfigure an SoC's power and performance profile.
The advanced prefetch engine is designed to analyze multiple concurrent request streams from clients to the memory, then determine which requests should be optimized or prefetched. The software analyzes multiple concurrent request streams by utilizing patented Memory Tracker Technology to create virtual request streams, optimize memory subsystem efficiency and analyze results.
In early benchmarks using mesh generation, neural network, finite difference, MP3 decode and stream benchmark, a reduction in read latency that ranged from between 71% to 78% was produced, resulting in an increase in CPU IPC and MFLOPs per second.
Available now, MRO is distributed as synthesizable Verilog RTL source code that includes a single clock domain, fully static design, push-button synthesis and example scripts, documentation, configuration utilities and a complete verification suite. The SIP compiles on any commercially available design tool. MRO supports industry standard AXI4 and OCP on-chip interconnect specification protocol interfaces, and Multi-Client Interface supports up to 16 clients and 16 memory channels.