High-Performance ADC Simulation at the CERN Large Hadron Collider

High-Performance ADC Simulation at the CERN Large Hadron Collider

Sponsored by Mentor Graphics

The ATLAS Experiment at the CERN Large Hadron Collider required the design of a custom ADC. The ADC developed for this application is a dual-channel 12-bit ADC test chip, in which each channel consists of four pipeline stages to resolve the four most significant bits, followed by an 8-bit successive-approximation-register (SAR) ADC.

Learn about the extensive chip simulations performed during the design phase that led to high confidence of success at the tape-out stage in this white paper

Mentor Graphics

TAGS: Analog Power EDA
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