While new successive approximation register (SAR) analog-to-digital converters (ADCs) were popping up all year with remarkable new levels of precision and conversion rates, there was less activity in the world of pipeline and delta-sigma (ΔΣ) architectures. In fact, up to the middle of October, only Texas Instruments was announcing new non-SAR devices.
In the first stage of a pipelined ADC, the sample-and-hold (S/H) samples the analog signal, and the flash ADC converts it to an M-bit digital code (Fig. 1). This code represents the most significant bits (MSBs) of the ADC’s final output. The same code is fed to the digital-to-analog converter (DAC), which converts code to an analog voltage. This voltage is subtracted from the voltage held by the S/H. The next stage in the pipeline samples and converts the resulting voltage. The number of stages depends on the required resolution and the resolution of the flash ADCs used in each stage.
ΔΣ ADCs feature a ΔΣ modulator and a 1-bit DAC (Fig. 2). The ΔΣ modulator consists of an analog integrator and a comparator, with feedback through the DAC. After the DAC’s output is subtracted from the analog input signal voltage, the resulting difference voltage is fed to the integrator and the comparator. The other input to the comparator is a reference voltage. The output of the comparator drives the DAC.
The process is clocked at a very fast oversampled rate, although the actual quantization time is comparatively long because the binary output stream from the comparator is a serial succession of ones and zeros. The ratio of ones to zeros is a function of the input signal’s amplitude. In the final step, a binary output representing the value of the analog input is obtained by digitally filtering and decimating this stream of ones and zeroes.
In early January, TI announced a new pipeline-architecture device, the eight-channel, 12-bit, 100-Msample/s ADS5295. Target applications include ultrasound, instrumentation, and communications. Its low power consumption and integrated multiple channels in a compact package make it attractive for very high-channel-count data acquisition systems. Output is via one or two wires of low-voltage differential signaling (LVDS) pins per channel.
At high sample rates, the two-wire interface helps keep the serial data rate low, allowing the use of low-cost FPGA-based receivers. Tight channel matching is accomplished by an internal reference. A low-frequency suppression mode, digital filtering options, and programmable mapping functions are also provided internally. There are low-pass, high-pass, and band-pass digital filter options too, as well as filters to remove dc-offset. Unit pricing is $70 in quantities of 1000.
In May, TI announced the ADS4449, a four-channel, 250-Msample/s pipeline device that enables receiver systems to support up to 125 MHz of instantaneous bandwidth in applications that must accommodate extremely small footprints such as multiple-input multiple-output (MIMO) basestations and munitions guidance devices (Fig. 3). TI also expects the ADC to find application in electrically scanned array (AESA) and other phased-array radars. Unit pricing is $199.85.
On the ΔΣ side, last March, TI introduced a converter for automotive applications such as battery monitoring systems in hybrid electric/electric vehicles (HEV/EVs) and for fuel or oil-pressure sensing. The 16-bit, 860-sample/s ADS1115-Q1 integrates a voltage reference, a programmable gain amplifier (PGA), a multiplexer, and an oscillator. It also has the industry’s only integrated programmable comparator, which makes it easy to implement over-voltage or under-voltage threshold monitoring. Unit pricing is $2.60.
And yes, you read that correctly. Three different ICs were reported with at-introduction “budgetary” pricing for 1000-unit quantities of, respectively, $70, $200, and $2.60 per unit. All devices came from the same supplier. The variation takes some getting used to. Consider budgetary pricing values to be indices of development costs versus potential sales volume.