System-on-chip (SoC) and system-in-package (SiP) solutions offer benefits in terms of component count and complexity. Thus, it’s important for designers to understand the pros and cons of each when choosing the most suitable solution, says Bill Saperstein, a system architect with AMI Semiconductor.
SoC solutions can contain analogue, digital, or mixed-signal circuits, and they feature IP that’s often in the form of a soft macro synthesised to the target silicon. IP may also take the form of a hard macro targeted to a specific silicon technology and process. Either way, “reusable” IP, which has been previously proven and characterised in silicon, is essential to successful SoC design.
A critical hurdle for SoC development is the integration of increasingly sophisticated IP into the design. Furthermore, for specialised hard macros, the IP may only be available in a limited number of processes. Integration also becomes more difficult if the IP modules don’t provide for common interfaces.
Once integration is achieved, major effort must be given to verification, which can take over 60% of the design cycle and require costly and sophisticated EDA tools. In addition, as chips become more complicated, there’s a need to push for more advanced silicon processes to attain smaller die size and lower power. These cutting- edge processes entail significant NRE costs, and even more costly EDA tools.
The SoC NRE challenge can be significant when including IP investment, EDA tools, and silicon processes. Then there’s the often long development time required for front-end design and verification as well as backend placement, routing, and timing closure. Put that all together, and SoC development costs can run into the tens of millions with extended development cycles.
System-in-Package
SiP solutions assemble active electronic components (package or die) of different functionality, plus other devices such as passives, MEMS, or optical components, in a single package.
In general, there are three technology types: module (single/ multichip), stacked die, and 3D packaging. Modules are standard packages incorporating one or more horizontally arranged die. They contain chiplevel interconnects (wire bond or flip-chip) and optional surfacemount passive and active components on a substrate that provides interchip connections, controlled impedance lines, and grounding structures, all in a protective casing.
Stacked-die packages consist of multiple vertically stacked die with chip-level interconnects to a substrate enclosed in a standard package format. And 3D packaging is a combination of standard pre-packaged devices or components using laminate, ceramic, flex, or lead-frame substrates stacked vertically with package-level interconnects.
A key advantage of SiP is flexibility of device integration. SiP also allows for complex or specialised chips that provide functionality difficult or impossible to integrate into a single SoC. For example, high-performance GaAs designs can be combined with standard CMOS digital chips for an RF application.
Usually, SiP development is shorter since the components don’t require as much design verification (at the functional level). Thus, the cost to develop a SiP design can be substantially lower than an SoC. Furthermore, if a complicated substrate is limited only to the SiP module, then fewer layers will be required on the system board. This reduces system costs, allowing changes to be focused on the SiP rather than the board itself.
There are, however, challenges facing SiP development, not least in terms of cost and development time for new packaging technologies. Although this technology has matured into the mainstream, it’s primarily offered by first-tier packaging and testing houses. Furthermore, many of the EDA tools for high-speed electrical/ mechanical system designs that would favour the SiP aren’t commercially available. Thus, they require in-house development. Current silicon design EDA tools don’t completely cover the mechanical aspects of SiP designs.
Another key challenge is the availability of known-good die (KGD) when trying to incorporate bare die onto a module’s substrate. Many IC manufacturers don’t offer KGD solutions as standard, typically because KGD produces a more challenging test flow and process than standard packaged parts. In particular, full functionality must be performed at the wafer level rather than at the package level.
The table offers a comparison of key criteria relating to SoC and SiP technologies. For those applications requiring lowest power, highest clock rates, and lowest costs, SoC seems to be a good match, even if new IP is needed. For those applications that need a fully functional, highly specialised module that can be easily integrated into a system, the SiP seems most appropriate. Localising different component technology within a SiP module reduces the complexity and cost of the system board, ultimately removing this design burden from the system engineer.
