Electronic Design


Interpreting A Difficult Equation
I read the article "Pay Attention To The Clock And Output Bus To Improve High-Speed ADC Design" \[June 26, p. 137\]. My division studies and produces payloads for satellites in experimental space applications. The subject of this article is very interesting for my application, but I don't really understand equation (1),

which describes the SNR due to the jitter clock. You get the ratio signal to jitter noise in terms of rms and I have done the calculus considering a sinus function with VFSR voltage peak-to-peak and frequency FIN, but I didn't find your expression. The term VIN (ADC input level relative to full-scale in dB) isn't clear, nor is its position in the equation.
Paolo Ramaioli
Laben S.p.A. Co., Italy

I'm glad you found interest in my article on ADC clock and output bus considerations in the June 26 issue.

Equation (1) in that article uses rms jitter because ADC data sheets specify jitter in rms. We specify rms because jitter isn't sinusoidal. The VIN term in that equation is input relative to full-scale and is in dBfs. It takes the form:

The 10(VIN/20) term in my article converts this to a percentage of VFSR. Of course, we can multiply this term by VFSR to get the input peak-to-peak percentage of full-scale.

I hope this answers your question. Thank you again for your interest in my article.
Nicholas Gray

Thanks For All Those Years
Thanks for your word of tribute to Bob Pease for his 10 years of Pease Porridge in Electronic Design. \["What's All This Perfect 10 Stuff Anyhow?," Sept. 5, p. 182.\] I have enjoyed reading the columns since they began 10 years ago and even kept up my subscription to the magazine after retirement, mainly so I could continue to read Pease Porridge. For many years I would clip each column from the magazine and file it for rereading later. Hopefully, Bob will keep writing the column for many years to come.
Don Schmidt

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