Scalable Noise Generator

April 9, 2009
Using some shift registers and exclusive OR gates, it is possible to construct what is known as a psuedo random code generator. Depending on what taps are used on the shift register, a sequence of up to 2^n-1 numbers can be generated before the sequence r

Using some shift registers and exclusive OR gates, it is possible to construct what is known as a psuedo random code generator. Depending on what taps are used on the shift register, a sequence of up to 2^n-1 numbers can be generated before the sequence repeats. If we feed the output of the shift registers into an A/D converter and look at the output, we will see what looks like white noise.

The noise produced by this circuit has a flat spectral distribution and can be considered white noise. However, instead of having a gaussian output characteristics, it is uniformly distributed. A snap shot of the output appears below:

Choosing the right taps is something of an art. There are lots of combinations that produce complete sequences but sometimes the sequences produce less than ideal spectral output. The taps chosen for this design were found in Spread Spectrum Systems by Robert Dixon. Code sequences of this type are used for Direct Sequence and Frequency Hopping modulation techniques. An FFT of our derived data sequence appears below:

The circuit itself is composed of two parts: 1) a 16-bit sequence generator followed by a 12-bit parallel A/D converter. The 100Khz clock is derived from a 555 timer. At turn on, the spare XOR gate is used to force some 1's into the shift register. Without this feature, the shift registers could wake up with all zeros and the psuedo random sequence would be all zeros - not very random.

The output of the DAC is followed by a 30Khz low-pass filter. This translates into an equivalent noise bandwidth of about 47Khz. The output voltage will swing between +/-5 volts. Increased dynamic range can be attained by increasing the gain of the op-amp. Upping the clock frequency with appropriate changes to the LPF will allow greater bandwidth. However be careful to not exceed the specifications on the DAC.

To maximize the output performance of the DAC, perform the following steps:

1. Offset Adjustment: with the data bus set to all 0's adjust R2 to give -5.00 volts output.
2. Gain Adjustment: with the data bus set to all 1's, adjust R1 to give a reading of +4.9976 volts.

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