The workhorse 8051 microcontroller will have a new class of job opportunities open to it thanks to the integration of an (E)ISA/PC104-compatible interface on the chip. Developed by Cybernetic Micro Systems, the P-51 (peripheral 8051) provides an 8051 core, plus all the standard 8051 peripherals and I/O lines.
The chip includes a full (E)ISA- or PC104-compatible interface that connects the microcontroller directly to a PC-motherboard ISA/EISA bus or a PC104 industrial PC bus. Also, the 8-bit microcontroller is no performance slouch. It can clock at 50 MHz to execute the 8051 instruction set. A future version will perform even faster by reducing the number of clocks required for each instruction from the current 8 to 12 clocks to just 4 clock cycles.
Also included are 8 kbytes of instruction-code RAM. The host can download code to be executed to the RAM when the P-51 is in Reset mode via a hardware strobe. The microcontroller remains in the reset mode until released via a software operation. After the reset mode is released, the processor will begin executing the code, starting at location 0.
Traditionally, the 8-bit 8051 has been used as a standalone controller, making it hard to tightly couple to a host system such as a PC. The P-51, though, provides a high-bandwidth interface that allows designers to use the controller as a closely-coupled peripheral resource in PC104 and PC systems. As a peripheral device, the P-51 expects to be reset by the host via a reset signal such as the (E)ISA RESETDRV signal, which resets all devices at startup.
In addition to the new bus interface, the P-51 includes breakpoint and single-step capabilities to ease the debugging of driver and application software. These features eliminate the need for expensive in-circuit emulation hardware, lowering the overall development cost. The breakpoint interrupts and single-step interrupt, as well as application-specific interrupts, all use a software-selectable IRQ (from IRQ-3 to IRQ-15). These interrupt lines are compatible with DOS, Windows, OS/2, and Linux IRQ support. And, the chip supports the EISA Refresh and IOCHRDY signals.
The P-51 enables Windows-based and Java-based programs to provide microsecond-accuracy response timing—a feature not possible with non-real-time Windows, which only supplies millisecond-class response. To provide all of the control capabilities, the P-51 includes a host-accessible control register that is mapped into the dual-port RAM address space. This register lets the host bring the P-51 in and out of reset via software, as well as drive the P-51 into the reset state via its Reset pin.
In the original 8051, multiple address spaces represented one of the more complex aspects that had to be dealt with. The P-51 is slightly more complex. On the 8051, the basic address spaces are only relative to the 8051, while a subset of the address spaces also are relative to the host on the P-51.
Though each address space starts at location/address zero from the 8051's perspective, the address as seen by the host is more complicated. That's due to a base-address register, whose contents are pin-selectable (and software-selectable). The base address can be specified via four pins that are connected through jumpers to ground or VCC. The high bits of the host address bus are compared to the bit value represented by the four pins. If there's a match, the P-51 chip is selected by the host, and its relevant address spaces become accessible to the host. The P-51 then can be mapped into the address space of an IBM-PC class computer and can function as an "intelligent memory."
The chip offers Timers 0, 1, and 2; Ports 0, 1, 2, and 3; dual data pointers; and math functions such as multiply, divide, and a new square-root operation (see the figure). It comes in a 100-lead package, so it can support the full PC-104 interface. In lots of 100 units, the P-51 sells for $15 each.
Cybernetic Micro Systems Inc., P.O. Box 3000, San Gregorio, CA 94074; Ed Klingman, (650) 726-3000; Internet: www.controlchip.com.