Many of today's SRAM-based FPGAs employ four-input lookup tables (LUTs) to implement basic logic functions. But for complex logic functions that expand beyond a single LUT or simple functions that occupy only a fraction of an LUT, the basic four-input structure can be very inefficient.
To overcome this problem, Altera Corp. has developed a novel structure formed from what the company calls "adaptive logic modules" (ALMs). These circuits enable adjacent logic functions to share logic. As a result, ALMs implement a given function with higher performance and greater efficiency than other FPGA architectures.
The ALM is the basic building block of the Stratix II FPGA family. Each module contains two adaptive LUTs. (See the block diagram) With up to eight inputs to the combinatorial logic block, one ALM can implement up to two independent functions, each of varying widths. One ALM also can form any function of up to six inputs and certain seven-input functions.
Along with the two adaptive LUTs, each ALM packs two programmable registers, two dedicated full adders, a carry chain, an adder-tree chain, and a register chain that all help to more efficiently use the ALM logic capacity. By enabling adjacent LUTs to share logic and inputs, ALMs reduce the logic resources required for any given function and the number of logic levels needed in a given critical path, permitting circuits to run faster.
In addition to the new logic structures, the just-released Stratix II family uses 90-nm design rules, making the devices faster than ever. Internal clock frequencies can hit 500 MHz, and typical system designs can run at over 250 MHz. Functions like 18- by 18-bit multipliers can run at 370 MHz. I/O ports can deliver 1-Gbit/s data rates with a new technology called dynamic phase alignment (DPA). DPA logic, which provides source-synchronous performance without consuming logic resources, simplifies pc-board layout and timing management.
The Stratix II FPGAs also pack many features available in the original Stratix family. These include the old TriMatrix memory architecture, the DSP building blocks, and the external memory interfaces. Yet thanks to the 90-nm process and nine levels of copper metallization, the chips offer twice the logic density and up to 9 Mbits of on-chip SRAM.
As for speed, the circuits can run 50% faster than the previous Stratix FPGAs. The higher-performance logic also enables the FPGAs to offer dedicated support for the latest high-speed memories—266-MHz DDR2 SDRAMs, 300-MHz RLDRAM II, and 200-MHz QDR II SRAMs—with sufficient bandwidth and I/O pins to support interfaces to standard 64-bit 168/144-pin DIMMs.
The Stratix II FPGAs also include advanced-encryption-standard-based nonvolatile 128-bit encryption technology. This development ensures that a designer's intellectual property used in the FPGA is secure from piracy.
Six initial devices are slated for the Stratix II line. The EP2S15, S30, S60, S90, and S180 contain 6240 to 71,760 ALMs and between 419 kbits and 9.338 Mbits. Each FPGA also packs phase-locked loops (PLLs) and DSP multiplier-accumulator (MAC) blocks—six PLLs and 12 MAC blocks on the smallest chip and 12 PLLs and 96 MAC blocks on the largest. User I/O pin counts range from 358 on the S15 to 1158 on the S180.
Altera will offer HardCopy implementations of the chips in addition to the RAM-based versions of the Stratix II FPGAs. The HardCopy versions supply a lower-cost option when systems go into volume production.
Version 4.0 of Altera's Quartus design software will support the Stratix II family. Incorporating many ASIC-like design capabilities, the software offers a comprehensive suite of optimization, verification, and system-level design tools. (For more information about the Quartus tools, see "Altera Updates Its Design Tools For Stratix II FPGAs," p. 36.)
The first device to be sampled, the EP2S16, will be available next quarter. It costs $150 each in lots of 25,000 units. Remaining Stratix II chips will be sampled late in the second quarter.