EE Product News

Clock Multiplier Lowers Boom On Jitter

Expanding the company’s family of SONET/SDH clock multiplier ICs, the Si5318 delivers jitter generation as low as 0.7 psRMS, said to be lower than OC-48/STM-16 jitter specifications. Like its siblings, the device employs DSPLL technology, which uses digital signal processing techniques to create an integrated PLL and a wide tuning range. The chip generates a single output clock in the 19 MHz or 155 MHz range from a reference input ranging from 19 MHz to 155 MHz. It also provides user-selectable loop filter bandwidths ranging from 800 Hz to 12.8 GHz, allowing users to match the level of jitter attenuation to the amount of clock cleaning required by the application. Available in a 9 mm x 9 mm CBGA, price is $32 each/1,000. An evaluation board, the Si5318-EVB, is also available for $350. SILICON LABORATORIES INC., Austin, TX. (877) 444-3032.


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