The semiconductor industry has experienced dramatic growth and technological advancement over the past several years. What was "leading edge" in 1994, with transistor features in the 0.5-µm range, gave way to even greater challenges just three years later, as the industry approached 0.25-µm technology.
This growth and development is in direct response to applications like electronic data processing, electronic games and toys, stereos, cellular phones and pagers, switching systems and satellites, military/aerospace, industrial, and automotive products. Each of these applications has specific IC-packaging needs, which has resulted in a plethora of options, ranging from low-cost, quad flat packages (QFPs) to expensive, high-performance multichip modules (MCMs).
While evaluating the various packaging alternatives, the designer must consider to what level that package is supported by the various pc-board manufacturers. On their side, many strides have been made as far as via size, line width, and spacing are concerned. Until recently, the IC-design and pc-board manufacturing industries worked independently. Now, rising levels of integration make it imperative that IC designers, package manufacturers, and the pc-board community work closely to reduce overall cost, enhance performance, and ensure the feasibility and manufacturability of the final design.
To that end, a number of technology roadmaps have been outlined to define the challenges ahead for the industry. The overall goal of these roadmaps is to encourage participants, at every level, to cooperate and realize each other's full potential to their benefit and the benefit of the end user.
The main issues driving component packaging today are thermal and electrical performance, real-estate constraints, and cost. The applications and systems typically dictate what's needed, with suppliers moving quickly in response to ever-shrinking time-to-market windows (Fig. 1).
The high-end microprocessors run at higher frequencies, and require thermally and electrically enhanced packages. These thermal enhancements come in the form of thermal vias, heat slugs, heat sinks, and component towers, while the electrical enhancements are usually provided through multilayer packages and in-package, capacitance-control features. Hermetic ceramic packages are popular for these applications.
For mid-range systems, performance is important, but so is cost. Therefore, thermally enhanced multilayer packages such as plastic ball-grid arrays (PBGAs) or QFPs are possible candidates.
For low-end and portable systems, cost and form factor are critical. Generally, surface-mount packages, such as QFPs, thin small-outline packages (TSOPs), and tape-automated bonding (TAB) technologies are used. The ideal component package is rarely obvious, however.
For many, the robust assembly capability of the BGA, which has I/Os situated underneath the package body, provides greater system capability than the QFP (Fig. 2). Also against the QFP is the fact that its I/O-count capabilities top out at 208, as anything in excess can stress the package's peripheral-lead arrangement. Yet, both the QFP and BGA can be thermally enhanced, allowing their use in a greater range of applications.
Increasing functionality and speed requires more power, more bond pads on the die, and more pins on the package. Fortunately, even with the increase in bonding sites, the I/O count in many packages is kept to a minimum through the use of decoupling capacitors within the package and on the die. Adding power and ground planes within the package further reduces the number of I/Os. In enhanced plastic packages, I/O counts may be higher to avoid adding extra layers, thus in-package capacitance is generally not feasible. For example, a microprocessor that has 168 I/Os in a ceramic package might require 196 I/Os in a plastic surface-mount package. Such conditions make the package characteristics very important to both the designer and the assembler.
During the 1960s, IBM and Delco practiced a totally non-packaged IC assembly method called flip-chip. This technology, which has risen in popularity as of late, places solder bumps, or connections, on the component bonding site, with the package attached to the substrate in a face-down fashion.
Known Good Die
The use of "known-good die," coupled with the determination that a die designed for wire bonding could be easily converted to an array format, has provided a new format that promises to provide the performance and thermal characterization needed by the industry--but in a die-sized package. One variation of these packages is the mini-BGA (Fig. 3). Many manufacturers throughout the world, including Hitachi and Intel, have licensed this design, which was standardized by the Joint Electron Device Engineering Council (JEDEC).
The mini-BGA is constructed using a flexible circuit, similar to TAB circuitry. The flex circuit is attached to the surface of an IC using a semiconductor-grade elastometer; its structure forms the basic redistribution layer or interposer. Flexible, ribbon-like bond leads of metal, such as gold or gold-plated copper or nickel, are bonded directly to the gold or aluminum pads of the IC. This allows a chip to be used in a QFP, where it is wire-bonded to a lead frame. It also could be repackaged in the smaller CSP configuration by having the interposer convert the peripheral bonding sites of the die to an array configuration.
The elastometer, or compliant polymer layer, serves to decouple the differential expansion of the silicon from that of the interconnecting substrate. This compliant layer, together with the S-shaped bond lead ribbon, effectively decouples the device from the strains of thermal expansion. The result is chip-size packages that are compliant in the x, y, and z directions. In addition, this facilitates testing and assembly, while enhancing reliability. Although Figure 3 shows just a single metal-layer construction, mini-BGAs can be fabricated with two metal layers for power and ground distribution, and with controlled impedance, making them suitable for the highest-level of electrical performance.
The most apparent advance in the semiconductor industry was the development of application-specific integrated circuits (ASICs). Higher clock rates, both on and off the chip, provided not only greater capability, but also greater challenges. To buffer increases in chip speed, new materials are being researched for wafer-level interconnections (as evidenced by the announcement from IBM and others to use copper wiring instead of aluminum). These advances may also have implications at the chip-to-substrate interconnect level.
Pressure is also being put on designers to find the most effective thermal management solution as well as the most effective software to model this high-level circuitry. The package size is already shrinking to meet the miniaturization requirements of hand-held products. All of this is taking place amid cries for lower cost.
One way designers have found to achieve the above requirements is to create custom ICs that are essentially systems for a specific application. Along with helping companies differentiate their products from their competitors', addressing the specific needs of a system allows the electronic designer to achieve greater performance without necessarily increasing semiconductor package size.
The arrangement of transistors, memory, and other logic functions on a single die provides a system architecture that is functionally cost effective. This points to the day when a total system in the application may be contained on a single chip. To achieve these goals, designers continue to ramp up the level of integration on each ASIC that they produce.
Because semiconductor manufacturers have historically driven the rest of the interconnect substrate advances, they have inherently managed their own futures. Still, in looking at ways to reduce package cost, that industry is more closely considering printed-board materials and manufacturing capabilities. Attaching a lead frame with wire bonding has long been a technique used for making small-outline ICs, SOPs, and QFPs.
Nevertheless, the robustness of BGA assemblies is behind a greater demand for that packaging configuration. Users wanting to avoid the flimsy leads found in packages with 0.4- and 0.3-mm pitches are requesting more array-type packages, both in standard and mini formats. To reach the cost parity necessary to move arrays into the mainstream, the semiconductor industry is exploring the use of organic substrates (Fig. 4).
And, because the semiconductor industry predicts the need for more I/Os, arrays will likely become the package of choice. Yet there are some hurdles to overcome. Package size and weight reduction are important. The coefficient of thermal expansion mismatch between the package and the board must also be addressed. What may be the final factor is is the cost per pin.
IPC's Interconnection Technology Research Institute has been working to develop new materials that will sustain the temperature excursions needed by the bare die. In addition, they have several projects in the area of microvia technology. Microvias are very small holes--150 µm or less--that can be produced through chemical or plasma etching, as well as lasers. The holes are then metallized to provide the interconnections through the core material (Fig. 5). Microvia technology uses standard organic substrates; the small holes can achieve the interconnection and redistribution from the periphery of the die to the array pattern.
As with most everything else, cost is the major hurdle. Users want faster microprocessors and ASICs that meet specific performance demands. Meanwhile, suppliers are stretching to meet integration requirements--the combination of memory and logic functions on a given chip--while giving users a package that is economical and can be easily interconnected. With the high level of competition, those companies that reach the market first tend to be the ones that obtain the necessary design-ins to recoup their investments. And, with the high cost of development, IC manufacturers require premium payback in the first year, with payback gradually reduced over time.
While payback cannot be overemphasized, manufacturers and designers can also look within to reduce development costs. One major offender is the manner in which the semiconductor industry works with the next level of interconnection, the dreaded "design thrown over the wall" scenario.
The interconnect industry has been criticized for not keeping up with levels of performance found in semiconductor dice. Some of this catch-up relates to the package itself, and some is related to the manner in which the I/Os of the chip were designed. But probably the most important factor is the pervasive "it's-not-my-problem" attitude. These philosophies must die, and designers at each stage of the manufacturing process must learn to work in closer harmony if they are to achieve the full potential that chip integration offers the end user.
How Will We Get There?
Many industries have developed technology "roadmaps" to identify where they are heading. Some roadmaps, from the organizations listed below, are particularly relevant to the characterization and use of semiconductors:
* NEMI (National Electronics Manufacturing Initiative)
* NTRS (National Technology Roadmap for Semiconductors)
* IPC (National Technology Roadmap for Electronic Interconnections)
* EDA (Electronic Design Automation companies)
NEMI's members are typically large OEMs (IBM, Delco, Motorola), that seek insight into future miniaturization, speed, power, and performance requirements. These companies represent the leaders in technology. Many of the products they market are handheld, small-configuration, and other battery-powered devices. The NEMI roadmap details challenges for the semiconductor and interconnection industries, whose products are ultimately combined into functional equipment.
The NTRS covers manufacturing capabilities and reduction of the size of the IC geometry (over time). It details future speed, functionality, and power requirements. In staying in front of designers by offering greater capability than they need, semiconductor manufacturers hope to maintain growth rates and continue to expand. Their strategy: By providing greater integration and faster speed, and taking appropriate measures for power and frequency, the only worries left for the designer are device cost and time-to-market.
Those who follow trends in new equipment releases know the product cycle pattern. About every six months a product is launched that offers greater functionality and capability. It usually wears a smaller price tag, and often comes in a smaller form factor. Miniaturization, in fact, is a key issue in many of the roadmapping feature concerns.
The IPC National Technology Roadmap for Electronic Interconnections merges the OEM needs outlined by NEMI, taking into account anticipated advances in semiconductor (NTRS) technology. It walks the difficult line in predicting how the printed board and assembly will fit.
Printed-wiring board (PWB) manufacturers and assemblers work closely to forecast methodologies for developing an interconnection structure that is both robust and performance-driven. Furthermore, assemblers are searching for a package that is easy to assemble, maintain, and replace on the substrates. IPC's roadmap also establishes the foundation for future board-level research.
Last, but not least, is the technology roadmap of the Electronic Design Automation industry. In fact, EDA suppliers are in even more of a catch-up mode than the PWB industry. Driven by needs for semiconductor automation, most of the original EDA roadmapping concerns focused on semiconductor requirements, including modeling, simulation, and process identification. There is no doubt that end-product applications are driven by microprocessors and custom logic devices. Nevertheless, the EDA roadmap now recognizes the need to more closely match the IPC and NEMI roadmaps, as EDA suppliers must provide tools not just for IC design flows, but also for board-design characterization.
As the industry approaches the 0.1-µm process for semiconductors, designers must give more consideration to interconnect signal transfer, noise margin, power leakage, and gigahertz signal speeds in the digital designs. Printed-board designers presently work around the inadequacies of existing systems, yet still can provide only marginal information to the PWB manufacturer. Often, it comes down to several follow-up discussions to pass on the complete product definition. Nevertheless, EDA companies hope to provide the automation tools that help the IC designer and the printed-board designer, as well as aid in the total simulation of a system that deals with the process characterizations impacting performance of the die.
The reason why roadmapping is so popular is that it works. The SIA roadmap is often credited for pointing out the steps that industry needed to take to win back world market share. In 1993, the IPC roadmap identified a need for small via holes. Today there are 18 variations of methods to produce microvias.
In the electronics industry, OEMs send designs out to fabricators and assemblers, providing the information needed to manufacture parts, thus underscoring a need for standardized design tools and documentation. Standards are often identified by the manufacturer and user, and as such, cross industry lines. This means standards-writing organizations must follow their lead.
In 1996, the industry worked together to develop J-STD-012, "Implementation of Flip-Chip and Chip-Scale Technology." This standard, supported by the Electronics Industries Association, IPC, JEDEC, MCNC, and Sematech, is really more of a roadmap, showing where the industry needs to be. However, it does identify standards that are necessary to achieve adequate communication among users and manufacturers. J-STD-012 names 20 standards that cross the boundaries of existing trade associations. Some examples of how semiconductor and interconnection companies work together include:
* J-STD-026--Semiconductor Design Standard for Flip-Chip Applications
* J-STD-027--Mechanical Outline Standard for Flip-Chip/Chip-Scale Configurations
* J-STD-028--Performance Standard for Construction of Flip-Chip/Chip-Scale Bumps
* J-STD-029--Test Method for Flip-Chip or Chip-Scale Products
* J-STD-030--Qualification and Performance of Underfill Materials for Flip-Chip and Other Micro-Packages
While technology roadmapping can help to bring industries closer together, it should be understood that while roadmapping identifies the challenges, it does not necessarily provide the solutions. It is the cooperation needed between different industries that will make those solutions a reality. In order to accomplish this, industries need to work together on intellectual property rights sharing. Participants in the development of electronic equipment need to work together for the total industry that they serve.