Advanced Analysis Solution Yields High-End Design Capability
Cadence Design Systems Inc.
(877)CDS-4911; fax (512) 349-7131; www.cadence.com
The PSpice Advanced Analysis solution enables analog/mixed-signal engineers to employ sophisticated design methodologies on the Windows NT and 2000 platforms. It provides integration with the company's Concept HDL and Orcad Capture industry-standard pc-board design capture tools. According to the company, this solution suits designers of components for large-volume consumer products, such as audio/video equipment and power supplies. In analog circuit design, this solution helps engineers tune the design topology so that it meets specifications. It also allows the designer to evaluate and improve design robustness and manufacturing yield. The PSpice Advanced Analysis software enables virtual prototyping. It eliminates hardware prototype spins. The system offers sensitivity analysis, optimization, yield analysis, and stress analysis capabilities.
This system is supported on Windows 98, NT 4.0 SP6a, and 2000. Pricing starts at $6600 for a one-year license.
Physical System Compiler Supplies Accurate Timing And Block Information
(408) 501-9600; fax (408) 501-9610; www.get2chip.com
TOPOMO is a physical system compiler that brings fully automated, accurate timing and block information to front-end IC design. This system integrates and automates block partitioning, block placement, global routing, and synthesis into one tool. TOPOMO automatically partitions a multimillion gate design into system-level blocks, based on actual timing and area, to achieve rapid timing convergence. The system concurrently places blocks, calculates wire capacitances, and creates a netlist that is driven by global interconnects. It has been used on customer designs ranging from 500,000 to 2 million gates with frequencies of 400 MHz in 0.18-µm process technology. The compiler generates and delivers all critical data necessary for good correlation (timing-accurate, gate-level netlist and placement directives) to back-end tools.
The system can be used with a variety of leading EDA technologies, including traditional back-end tools and modern place-and-route tools. TOPOMO costs $200,000 for a one-year license.
Transistor-Level Solution Permits Memory, Mixed-Signal Verification
NanoSim is a transistor-level solution for memory and mixed-signal verification. It combines best-in-class circuit simulation technologies. It also features tight integration with the VCS Verilog simulator to deliver high-speed, high-capacity verification of complex chip designs such as SoCs with analog, digital, and memory subcircuits on a single chip. This solution further enables flow by supporting Verilog-A, the industry-standard analog behavioral modeling language. NanoSim handles multimillion transistor designs and enables engineers to perform both power and timing analysis in a single simulation run.
The system uses the company's Hierarchical Array Reduction (HAR) technology to efficiently simulate large memories made up of hundreds of millions of transistors using user-specific vectors. Integrating seamlessly with an existing design flow, NanoSim shares the same commands, scripts, and libraries as PowerMill and TimeMill. NanoSim costs $81,000 for a one-year technology subscription license.
Coverification Products Optimize Embedded Software Debugging
Axis Systems Inc.
(408) 588-2000; fax (408) 588-1662; www.axiscorp.com
The Xpert family of hardware/software coverification products enables software designers to debug embedded system software before hardware prototypes are available. According to the company, these products increase verification productivity for both software and hardware designers. In the Xpert system, the company's patented ReConfigurable Computing (RCC) technology is extended from its original use in logic simulation, simulation acceleration, and system emulation to hardware/software coverification and embedded software debugging. The Xpert family enables software debugging with accelerated RTL processor models. It also enables instant tracing of software code execution. The system features instant resuming of software execution from any point in time.
For pricing and availability information, contact the company.
Full-Chip Simulator Handles Flat And Hierarchical Designs
Celestry Design Technologies Inc.
(408) 451-1210; fax (408) 451-1211; www.celestry.com
UltraSim is a transistor-level circuit simulator that offers timing, power, noise, and reliability analysis. This fast simulator handles flat and hierarchical designs. According to the company, UltraSim is the first commercially available sign-off simulator to offer simulation of 1 billion-transistor memory circuits. It provides full-chip capacity for memory, logic, and mixed-signal designs with built-in reliability simulation. This device eliminates the need to use multiple simulators, analysis tools, and additional power and reliability tools.
UltraSim is a Spice-precise simulator that offers power and reliability analysis. It also features accurate device models and easy integration into an existing design flow. According to the company, the simulator's run times match or exceed known alternatives with near-Spice accuracy. It has simulated a 50 million-transistor SRAM circuit in less than 40 minutes. It simulates over a billion transistors in less than an hour. Beta versions of UltraSim for Sun Solaris and Windows NT operating systems are available now. Production versions and an HP-UX operating-system version will ship soon. Pricing starts at $50,000, depending on configuration, options, and model.