HDTV on a 2-in. screen? Such a concept may challenge North American readers as the ultimate example of putting 10 pounds of goods in a five-pound sack. But Europeans, more accustomed to public transit and consistent phone and digital broadcast standards, may see the point. People in Japan already do. Two interlinked phenomena there are driving early demand for low-power, high-performance analog-to-digital converters (ADCs), which may eventually knock that five-pound-sack quip into orbit. Millions of Japanese commuters insist on using cell phones in subway tunnels and high-rise canyons. And, they want delivery of HDTV broadcasts. Such ubiquity depends on micro- and pico-cellular basestations and broadcast repeaters.
Recognizing this unfolding market, Linear Technology just introduced the first six members of a new family of 3.3-V ADCs for next-generation wideband CDMA (WCDMA) and HDTV broadcast/production applications. Before getting into the specifics, though, it's instructive to look at the technologies involved and how they drove Linear to develop the ADCs.
Low-power dissipation was a prime mover. While high-speed ADCs have always played an important role in basestation receive (Rx) and transmit (Tx) paths, cool running becomes essential for micro- and pico-basestations in metropolitan regions. To date, the limited ability to remove heat from the system has often proved the bottleneck for integration density.
In terms of performance, earlier baseband receivers used dual ADCs to sample demodulated I and Q signals, which are relatively close to baseband. Now, the trend is to support multichannel transmissions through a single Rx path by directly sampling at the IF. Rates of 65 or 80 Msamples/s are required at the 14-bit level.
In the Tx path, power-amplifier (PA) nonlinearity limits system-level performance. The old approach used analog techniques like feed-forward to control linearity. Instead, today's approach digitally pre-distorts the programmable-amplifier input using a fast feedback path, which includes a high-performance 12-bit ADC that can handle 125 Msamples/s. To reduce the number of stages needed to down-convert the RF output, the trend is toward sampling at a higher IF frequency. Since target IF frequencies from 100 to 200 MHz are already common, the ADC must have excellent under-sampling performance (see figures 1 and 2).
On the HDTV side, each TV channel's broadcasts require a network of wireless repeater stations and gap fillers positioned throughout the coverage area, in addition to traditional transmitters and receivers. Beat cancellers also are needed in some geographies to remove interference with existing analog broadcasts. Sample rates for broadcast ADCs in these systems depend on the number of adjacent channels to be processed simultaneously.
Eight 6-MHz channels require rates above 100 Msamples/s at the 12-bit level. Because the RF transmission band spans approximately 500 to 700 MHz, any scheme that directly samples this RF signal must maintain good pass-band flatness and distortion performance at extremely high frequencies.
Linear's ADCs also are intended for HDTV cameras, particularly battery-powered mobile cameras. Based on the camera CCD resolutions of the two Japanese HDTV standards, ADCs for standard definition require 25 Msamples/s, and high-definition ADCs require 80 Msamples/s.
First chips arrive
Linear's initial chips, in what will ultimately be a range of 24 parts, comprise 10- and 12-bit converters with speeds from 80 to 125 Msamples/s and power consumptions from 366 to 660 mW. The top performer, the 12-bit, 135-Msample/s LTC2224, specs out at a 67-dB signal-to-noise ratio (SNR) (typical) up to a 170-MHz input. It features a 775-MHz bandwidth and 77-dB spurious-free dynamic range (SFDR) up to a 250-MHz input. Other significant advantages include the option of using much smaller surface-mount capacitors, rather than tantalums, for bypass.
All of these parts come in 7-by-7 QFN packages with a common pin-out. The table shows organizations, speeds, and prices for 1000-unit quantities.
Analog circuits don't scale as well with shrinking process-technology feature sizes as digital circuits do. Thinner oxides demand lower operating voltages, and ADCs traditionally depend on 2-V input swings to achieve dynamic range. Linear believes shrinking process technologies are useful at least as long as 3.3-V operating voltages are possible.
The company uses Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC) for the LTC2224 family. (Its captive fab capabilities stop at 0.6 µm.) But it credits its own design engineers with reducing bias currents and taking advantage of the high transconductance (gm) offered by shorter channel lengths to squeeze 5-V CMOS-equivalent performance from 3.3-V parts that consume little more than one-third the power of the higher-voltage ADCs.
Unlike digital CMOS circuits that dissipate mostly dynamic power, most of an ADC's power consumption comes from the static current used to bias amplifiers and comparators. Shorter channels mean a higher gm and lower parasitic device capacitance. In turn, gm determines settling speed for each stage in a pipeline ADC, and therefore maximum sampling rate.
Thus, shorter channels enable higher-speed operation for a given total bias current. At the same time, lower supply voltages reduce total power dissipation even if the analog bias current remains the same. By scaling the process, Linear's EEs had the flexibility to increase speed at a given power level or reduce the power for a given speed.
But if the supply voltage is reduced too much, the corresponding reduction in input voltage range results in less signal power, and SNR falls. For the products Linear is introducing, SNR is competitive with 5-V ADCs. The company says it's not clear how far scaling can continue to go, but designs will probably involve scaling channel length for at least a few more generations.
|SPECS AND PRICES FOR THE LTC22XX SERIES|
|Part number||Resolution (bits)10||Speed (MSPS)||Power (mW)||1k price (US$)|
|All parts are in production now|