A new self-aligned gate structure used in a NAND-based flash memory allows designers at Toshiba Corp. and SanDisk Corp. to craft NAND flash-memory chips with capacities of up to 4 Gbits. The gate's ability to self-align to the active area of each storage transistor makes it possible to minimize the area for each device, since layout margins due to manufacturing tolerances can be kept to a minimum. Able to support both 2-Gbit single-bit/cell and 4-Gbit multilevel cell (2 bits/cell) designs, the self-aligned structure can be scaled to use 90-nm and smaller design rules. This will lead to devices with even higher densities. The companies plan to use the new structure in NAND flash-memory chips that will be sampled in the first half of 2004. For more, go to www.toshiba.com/taec or www.sandisk.com.