Bridge Lessens Video Preprocessing Load On Host Processors

Bridge Lessens Video Preprocessing Load On Host Processors

The T358749XBG HDMI-to-MIPI bridge IC developed by Toshiba Electronics Europe (TEE) integrates video de-interlacing and video scaling, enabling HDMI video streams to be recognized and read directly by application processors. Moreover, the chipset provides a quick path to other processor application areas without having to perform time-consuming processor redesigns.

By providing on-chip support for video preprocessing of video de-interlacing, video scaling, and video format conversion, the T358749XBG replaces software processing and reduces memory bandwidth on host processors for consumer electronics.

The IC supports HDMI 1.4 for video format resolutions of up to 1080p at 60 frames/s, as well as HDCP 1.3 and 3D. Maximum HDMI clock speed is 165 MHz. The MIPI CSI2 output video interface offers four data lanes at a maximum 1-Gbit/s/lane link speed.

The interface bridge IC also supports multiple audio interfaces, including I2S, TDM, S/PDIF, and MIPI Serial Low-power Inter-chip Media Bus (SLIMbus).


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