Electronic Design

Self-Aligned Split-Gate Process Cuts Flash-Memory Cell Size By 40%

A self-aligned process technology that cuts the size of flash-memory cells by 40% has been developed by Silicon Storage Technology (SST) Inc., Sunnyvale, Calif. According to the company, this split-gate architecture designed for flash-memory cells is the first in the industry to offer self-alignment. It substantially reduces the cell's size, and it also assures scalability for smaller geometries. Using this NOR-type architecture, SST developed the SuperFlash cell in conjunction with licensee IBM.

The SuperFlash technology utilizes a reliable thick-oxide process with fewer manufacturing steps. This produces a low-cost, nonvolatile memory solution with excellent data retention, SST says. The architecture facilitates a simple and flexible design suitable for high performance, high reliability, and small- or medium-size in-system or off-system programming applications. It offers a variety of densities in a single CMOS-compatible technology as well.

SST believes the SuperFlash will quickly lead to cutting-edge process geometries of 0.13 µm and smaller. The company has demonstrated the cell for three of its foundry partners—Sanyo Electric Co. Ltd., TSMC-Acer Semiconductor Manufacturing Co., and Taiwan Semiconductor Manufacturing Co. (TSMC) Ltd. Products based on a 0.18-µm self-aligned SuperFlash cell should begin shipping early next year.

Licensees TSMC and Sanyo are currently using the cell for embedded applications. TSMC offers both the conventional and the self-aligned SuperFlash cell through its EmbFlash processes.

For more information, contact SST at (408) 735-9110, or go to www.ssti.com.

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