Electronic Design

Transistor Promises Dense, Fast 30-nm ICs

Maintain device performance at 30 nm by surrounding the source-drain region of a transistor with three gates.

Researchers at many companies have proposed a host of different transistor structures that can deliver high performance as dimensions shrink to 60 nm and below. At June's Symposium on VLSI Technology and Circuits in Kyoto, Japan, Intel Corp. showed its latest 3D device structure.

This triple-gate transistor overcomes some of the fabrication limits of earlier dual-gate 3D structures. Fabricated with a fully depleted CMOS process, the transistors achieved a drive current that was 1.2 times that of a standard planar transistor of comparable gate width at dimensions down to 30 nm.

As transistors get smaller and operating voltages drop, it becomes a challenge to ensure that device leakage current doesn't increase, especially while maintaining a high drive current. The common planar transistor used in all CMOS circuits today has a single gate over the source-drain region, and it becomes pretty leaky as dimensions drop below 90 nm.

In the triple-gate structure, gates surround the source-drain region on three sides. Because the multiple gates allow the transistor to be fully turned on, designers can achieve a maximum drive current of 1.23 mA/µm with a 1.2-V gate bias (see the figure). The device also has an extremely low leakage current—just 40 nA/µm with no gate voltage. The combination of high drive and low leakage sets a new performance record for NMOS transistors.

Previous research efforts employed the finFET dual-gate structure, which was hard to fabricate because the width of the source-drain region had to be narrower than the gate length. Typically, the gate length is the smallest feature. So, the source-drain width had to be smaller than the smallest dimension that would otherwise be fabricated.

The tri-gate design eliminates this problem. Now, the source-drain width only needs to be comparable to the gate length, making it easier to fabricate. Aggressive polysilicon lithography and etch schemes are used to get the proper dimensions. Designers then impurity-dope (boron) to set the appropriate threshold voltage.

Intel's researchers feel that this structure is a strong contender for its 45-nm process, which is expected to be used for production in 2007. The company has already moved the tri-gate transistor from research to the development phase. Experimental devices have been fabricated at the company's 300-mm wafer fabrication facility in Hillsboro, Ore.

Intel Corp.

TAGS: Intel
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