Electronic Design

EDA Roundup

A 70% Logic performance edge can result from the use of Xilinx's latest revision of its Integrated Software Environment (ISE) in progamming Virtex-4 and Spartan 3E FPGAs. ISE 7.1i incorporates ease-of-use features such as a new design-summary view and message filtering, both of which reduce the need for designers to search through detailed report files. A Technology Viewer displays post-synthesis results in a schematic view that's easy to navigate. Two new simulators are incorporated: ISE Simulator and ModelSim Xilinx Edition-III. Mentor Graphics' Precision Synthesis tool is tightly integrated into ISE 7.1i, so users can invoke synthesis directly from the ISE Project Navigator. Prices for ISE 7.1i range from $695 to $2495. A free downloadable version is available now. See www.xilinx.com for details.

Version 2.1 of the OCP-IP specification will be available at the end of the first quarter from the Open Core Protocol International Partnership. The specification will now include profiles for the most commonly coupled Open Core Protocol (OCP) features and an advanced tagging scheme for enhancements in out-of-order processing. Profiles help designers learn the protocol more quickly by recommending sets of OCP features that are typically used to solve common design problems. Unlike threads, which enforce no ordering restrictions, tagged transactions ensure that the system respects read/write hazards. For info, visit www.ocpip.org.

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