As cellular phones incorporate the multi-function capabilities that enable web-access and digital-camera functionality, their supporting memory subsystems grow increasingly complex. For engineers in today's cell-phone market, one of the main design challenges is to meet the demands for higher density and performance memory. Of course, they must do so at a lower cost and in a smaller space. At the same time, designers must identify a flexible solution to accommodate the need for low-end, mid-range, and high-end configurations.
Major design changes to the overall phone design may not be part of this solution. The cost and performance tradeoffs for different densities and types of memory must be balanced for specific handset designs. This is the only way to optimize the overall memory subsystem so that it best meets these conflicting requirements.
Previous "talk-only" mobile phones utilized 4 to 8 Mb of low-power SRAM for working memory and data storage (phone numbers, call logs, messages, etc.) backed up by button battery. For code storage, they used 16 Mb of NOR Flash or E2PROM. As phones became smaller and feature sets grew, multi-chip packaging (MCP) was developed. In a single package, it combined a 4-Mb SRAM die with an 8- or 16-Mb NOR Flash chip. The result was a reduction in space requirements for cell-phone memory.
In today's rapidly evolving cellular market, however, memory density has increased to support a diverse range of cell-phone applications. Consumers now demand feature-rich phones. These devices perform Internet browsing, text messaging, games, the downloading and playing of music, and digital-camera functionality and applications (including the ability to take, transmit, receive, and display photos). Such applications have caused an increase in the complexity of memory requirements.
Typically, cell-phone manufacturers now use 8 to 16 Mb of low-power SRAM for data backup; 32 to 128 Mb of Pseudo-SRAM (PSRAM) for the working area of the system; and 64 to 128 Mb of NOR Flash for bootable code storage on basic phone programs. They also employ 128 to 256 Mb or more additional memory—often NAND Flash—for application software and the storage of huge data, such as pictures and music (FIG. 1).
Meanwhile, handset size continues to shrink. The space that's available for the memory subsystem is the same or even less than it was previously. Today, multi-chip packages are available to combine a complete, complex memory subsystem in a single, small package. For example, a ball-grid-array (BGA) package with five stacked memory chips can be as small as 9 3 12 3 1.4 mm, depending on the specific memory configuration. Semi-custom combinations of two, three, or four types of memory—with stacks involving up to five or six chips—also are being combined in a single package. Technically, up to nine layers are now available in a stacked MCP product with higher stack variations on the horizon. And MCP uses standard package technology like gold bonding wire, which doesn't require an additional investment for a mass production line.
Memory-capacity requirements are driven by the increasing diversity of applications. For another view of the application and on-board memory trend, examine the combined total RAM plus Flash-memory requirement for various cellular-phone applications. Such applications include e-mail, Internet browsing, Java applications, camera/movie capability, and music playback (FIG. 2). The need for memory to support games, Internet browsing, e-mail, and camera functionality has grown at a much faster rate than was originally anticipated.
Before detailing the mix and density of memory chips for a specific handset design, it's important to consider the basic memory architecture. Two leading alternatives currently exist. The first option is a higher-density, higher-performance version of the conventional NOR+SRAM memory architecture. Often, it uses some combination of NOR+PSRAM+NAND. The other alternative is a newer, lower-cost solution that uses NAND plus low-power SDRAM. This latter option offers interesting performance advantages.
The conventional memory architecture for multi-function cell phones typically uses NOR Flash for code storage, PSRAM for work space, and NAND Flash for data storage. In some markets, SRAM is used for backup (FIG. 3). Designers often build upon the conventional cell-phone memory architecture by increasing the density of the NOR and PSRAM. For data storage, they add NAND Flash because NAND Flash has the lowest cost per bit.
To achieve improved system performance, even memory vendors have begun supporting Burst NOR and Burst PSRAM. The advantage of the Burst architecture is that it doesn't require major software changes. As a result, it helps to shorten development time and testing requirements. Such an architecture supports a reasonable speed while achieving sufficient performance. It also demands relatively low power consumption.
The new lower-cost alternative replaces NOR Flash for code storage with NAND Flash. Using a shadowing architecture, it brings stored code from NAND Flash into SDRAM for working memory (FIG. 4). When it's used with chip sets that support NAND for code storage, low-power SDRAM (with a typical speed of 83 MHz and up) combines with NAND-Flash memory to provide a cost-effective, high-performance solution for cell-phone memory subsystems. In addition to its much smaller cell size, NAND costs significantly less than NOR. Thanks to its significantly faster programming and erase times, it also can provide an overall performance improvement.
NAND is used for both code and data storage, while the low-power SDRAM is utilized for memory workspace. With the shadowing architecture, the code and data to be processed is loaded from NAND directly into SDRAM. This approach boasts significantly lower cost and faster speeds. Such functionality is beneficial to newer multimedia applications. The disadvantage is that it requires a major software change from the conventional approach. Often, this change translates into a longer development time for initial designs. But chip-set vendors are starting to support this feature in their products, so cell-phone designers don't need to worry about this too much.
Both memory architectures can be scaled to provide similar solutions with different memory densities. As a result, designers can easily create low-end, mid-range, and high-end variations of a basic phone design without having to make major changes to the memory subsystem. Different configurations of stacked MCPs also can be used as needed. They will support the features that are provided on different handset models.
To help designers evaluate the pros and cons of these memory architectures, let's take a more in-depth look at their performance characteristics and tradeoffs:
Traditionally, NOR-Flash memory has been used for code storage in mobile phones. It offers fast random read speeds (typically 65 ns) and boot capability. It is designed to execute code directly out of memory.
The features of NOR Flash are well suited to the random-access requirements of code storage. This memory architecture achieves random access by connecting the memory cells to the bit lines in parallel. If any memory cell is turned on by the corresponding word line, the bit line goes low (FIG. 5). Because the logic function is similar to a NOR gate, this cell arrangement results in NOR Flash.
NOR-Flash densities haven't kept pace with the density requirements of cell phones, however. This architecture's relatively large cell size (10F2, where F = design rule) has kept NOR Flash at a higher price than NAND Flash in cases of the same density. Existing MLC NOR Flash attempts to narrow this gap in cell size. But MLC NAND, which is in production now, appears to widen this gap. As a result, many cell phones continue to use the 32 to 128 Mb of NOR for the cell-phone operating-code storage. To support other functions, they turn to alternate types of memory.
The advantages of NOR Flash are defined by high-speed random access and the ability to program at the byte level. Its disadvantages include the slow programming of large data blocks and a slower erasing speed (typically 700 ms per block). By comparison, NAND has an erase speed of 2 ms per block (SEE TABLE).
Initially, Toshiba Corp. developed NAND Flash as a solid-state replacement for magnetic memory. To keep the cost per bit as low as possible, NAND Flash features a much smaller cell size than either NOR Flash or other nonvolatile memory. The NAND-Flash cell contains an array with either 16 or 32 memory transistors in series. This cell array has one memory transistor and two select transistors per each NAND chain of cell. Every transistor in a NAND chain of cell can share each source or drain area and reduce the number of contacts. This technology realizes a small cell area without scaling down the device dimensions.
In a consumer-electronics application, one of the most important characteristics of memory is the bit cost. In the case of a semiconductor memory, the bit cost is dependent on the memory cell area per bit. The cell area of NAND Flash is much smaller than the cell area of NOR Flash. As a result, NAND Flash has the potential to be less expensive. In addition to the cost, NAND's smaller cell size enables very huge-density nonvolatile memory of 1 Gb and up.
Because of its low cost per bit and higher-density part availability, NAND Flash was initially an attractive addition to the cell-phone-memory subsystem. It was used to store additional programs and data. Now, multiple cell-phone chip sets include support for NAND Flash. Consequently, some cell-phone manufacturers are using a combination of NAND plus low-power SDRAM to handle all of the cell phone's memory requirements. Chip sets already are capable of booting up in the system using NAND Flash and SDRAM without NOR Flash.
Conventional NAND Flash requires the chip-enable signal to be asserted low during the entire read cycle. This move prevents the processor from communicating with other devices on the same bus. NAND Flash for cell phones has a feature called "Chip Enable Don't Care," which allows the chip-enable signal to be de-asserted during the read busy period. The microprocessor can then communicate with other memory devices on the same bus, such as SRAM, PSRAM, or NOR Flash without hardware changes.
Meanwhile, the NAND Flash retrieves the information that was requested. This feature allows the read command to continue even if the chip-enable signal is de-asserted. It also permits the processor to communicate with the I/O device during the read busy period.
Referring back to the table, the advantages of NAND include high-speed programming (write capability) and high-speed erasing. Unfortunately, NAND also has slower random access and no capability for byte-level programming. The access time for NAND is 50 ns for a typical serial-access cycle and 25 ms for an initial random-access cycle. Compare that number to 70 ns for a NOR-Flash random-access cycle. When huge data like a digital camera picture is read out, there is no significant difference between them. When a typical program and erase sequence is compared for NOR and NAND Flash using a 64-KB block, NAND outperforms NOR by a wide margin (33.6 ms for NAND compared to 1.23 sec./block for NOR).
To complete the comparison of the memory architectures, the characteristics of the workspace memory must be reviewed. Initially, SRAM was used for cellular handsets. Now, it's rapidly being replaced by PSRAM in conventional architectures. With the development of low-power SDRAM, PSRAM's higher performance and low cost have made it an attractive alternative.
Low-power SRAM is very popular because data in a cell can be kept statically without the external refresh operations. Plus, battery life is an important criterion for mobile products. At 5-µA standby current, the very low power consumption of SRAM is very helpful to designers.
An SRAM memory cell is equivalent to a flip-flop latch circuit, which is composed of four or six transistors per cell. As a result, SRAM has a relatively bigger chip size. This size affects the cost per bit. To address this matter, memory vendors have developed Pseudo SRAM (PSRAM).
PSRAM comprises a DRAM memory cell, which has one transistor and one capacitor per cell. This design enables PSRAM to achieve a lower cost per bit. It also integrates a refresh-control circuit. As a result, the system doesn't have to manage complicated refresh operations. PSRAM is available with similar access times as SRAM (typically 65 ns and faster random-access times). To achieve higher performance, PSRAM also supports Page mode and Burst mode.
PSRAM offers the advantages of lower power consumption and lower standby current. LP SDRAM, on the other hand, is faster. It boasts speeds of 83 to 133 MHz compared to the 65-ns asynchronous access read for PSRAM. Compared to 128 Mb for PSRAM, LP SDRAM also is available in higher densities—up to 512 Mb today.
In the PC market, synchronous DRAM (SDRAM) is a very popular technology. Many processors support this interface, which can perform at frequencies of 133 MHz or above. To support many additional features, cellular phones are beginning to use higher-performance memory products. Power-consumption-wise, greater than 100 MHz is overkill for cell-phone systems now. But new features in future phone systems may need the high performance of random-access memory (RAM), such as Burst PSRAM or low-power SDRAM.
To select the optimal configuration for a cell-phone memory subsystem, designers must balance tradeoffs in cost, performance, power consumption, density, and availability. That way, they can best fit the requirements of a specific design. In general, memory requirements in high-end cellular handsets have increased dramatically to support new applications. As a result, multiple types of memory are needed to address the phone's code storage, working memory, file, and additional application-storage requirements.
To meet the space constraints of today's ever-smaller handsets, many manufacturers have turned to multi-chip packages. They can then obtain a complete memory subsystem in a single component. Today, traditional NOR+SRAM memory solutions for cell phones are being replaced by NOR+PSRAM+NAND solutions. A new architecture using NAND+LPSDRAM now offers advantages in both cost and speed.
Toshiba America Electronic Components, Inc.
9775 Toledo Way, Irvine, CA 92618; (949) 455-2000, www.toshiba.com/taec.