A reconfigurable compute fabric (RCF) based on an array of DSP cores promises flexible system solutions for wireless basestations and other communications applications. This architecture, developed by Morpho Technologies and enhanced by Motorola, provides a cost-effective and programmable alternative to ASIC- and FPGA-based basestation subsystems. The ability to customize the array's operation via software will let designers quickly bring new applications to market.
Motorola, who has licensed the architecture, expects to release details of an RCF commercial implementation late in the second quarter. The initial chip will include 16 DSP cores interconnected with a programmable fabric, a RISC controller, memory input and output buffers, and some routing and peripheral logic.
Each DSP compute element contains a multiplier-accumulator and other compute resources and instructions typically associated with DSPs. A very flexible, high-bandwidth interconnection fabric links these elements. A proprietary RISC controller on the chip serves as a control-plane processor, coordinating the operation of all the DSP engines. The array of 16 DSP cores and the fabric is, in itself, also a core—perhaps a better name would be a supercore. In performance-intensive applications, multiple "supercores" can be co-integrated to form a much larger computational array that's interconnected with a flexible routing scheme.
Designers can program the RCF with a combination of C and assembly language. By downloading different software, designers can change the function that the array executes, update the program to fix bugs, or add new functions to an existing feature set. Motorola is also developing a library of software modules and support tools to enable designers to rapidly bring applications up on the RC. MetroWerks, a Motorola subsidiary, has developed an integrated development environment that will let designers quickly develop and test new code.
For details, go to www.morphotech.com, www.motorola.com/smartnetworks, or www.metrowerks.com.