Support for the LatticeECP-DSP and LaticeEC FPGA families is now included in version 4.1 of the ispLEVER design tools suite. The suite includes tools for design entry, project management, design fitting, place and route, floorplanning, device programming, on-chip logic analysis, and more.
Enhancements to Version 4.1 provide users with a simple upgrade path for designing with the new FPGA families. It improves the design libraries and fitting engines for all Lattice FPGA families and adds support for the ispXPGA-E FPGAs and ispGDX2-E programmable crosspoint switches. The suite also includes new versions of third-party synthesis and simulation tools from Synplicity and Mentor Graphics.
On top of that, the suite now supports the Linux operating system for the first time. The suite wil be offered on the Red Hat Enterprise Linux Version 3 operating system.
The tools include DSP blocks for use in the Matlab/Simulink DSP design environment. These blocks can be used to build DSPs within Matlab/Simulink and then exported in HDL that's optimized for the LatticeECP-DSP FPGA architecture.
The LatticeECP-DSP devices, which aim at high-performance DSP applications, provide up to a 50% performance and 75% logic utilization boost over competing low-cost FPGAs when implementing common DSP functions. LatticeEC FPGAs are slated for general-purpose FPGA applications.
The ispLEVER 4.1 suite comes in a variety of PC-, UNIX-, and Linux-based configurations. List prices begin at $995.
Lattice Semiconductor Corp.