EDA Tool Maps Complex ANSI C And SystemC Algorithms
Version 2.2 of the AIRT Designer architectural synthesis tool suits the design of ASICs and high-density FGPA system-on-a-chip (SoC) implementations of low-power DSP applications. These include MPEG4, turbo codes, and IMT-2000 for W-CDMA. It lets designers derive and explore multiple hardware architectures from system-level, fixed-point SystemC, and ANSI C algorithms.
According to the company, the AIRT Designer 2.2 gives designers the flexibility to achieve optimized SoC implementations of DSP algorithms that will be used in 3G coprocessors. It allows DSP-based system designs to be done in MATLAB, SPW, or COSSAP and taken to a synthesizable Verilog or VHDL description using the SystemC or ANSI C languages. Floating-point ANSI C code can be refined to fixed-point SystemC code either manually or automatically, using tools such as Synopsys' CoCentric Fixed-Point Designer. The fixed-point SystemC description is then read directly by the EDA tool.
The tool comes with a predefined library of data-path resources, including adders, multipliers, ALUs, and registers. Designers can create multiple libraries with specialized resources and resources that execute several operations in one clock cycle.
AIRT Designer 2.2 is available now with several different pricing alternatives. Pricing starts at $45,000.
Frontier Design, Abdijstraat 34, 3001 Leuven, Belgium; +32 16 39 14 11; fax +32 16 40 60 76; www.frontierd.com.
PLI And FLI Code Generators Support Mixed-Language Simulations
The System Compiler incorporates fully automated Verilog programming language interface (PLI) and VHDL foreign language interface (FLI) code generators to support mixed-language C++ and VHDL/Verilog simulations. It is designed to support the needs of designers who want to use both C++ and VHDL/Verilog in their design flows.
This functionality allows users to verify their C++ models concurrently with Verilog or VHDL models using their current HDL simulator at any point in the hardware design process. After deciding which blocks will be co-simulated with Verilog, the designer sets an option at compile-time to specify that PLI/FLI code will be generated instead of HDL. By fully automating the task of generating the PLI and synthesizing C++ into HDL, System Compiler allows system designers to model with C++ as part of the flow without worry about verification or implementation.
The PLI and FLI code-generation capabilities will be extended to all present and future System Compiler users. The System Compiler costs $95,000.
C Level Design Inc., 3425 S. Bascom Ave., Ste. 230, Campbell, CA 95008; (408) 369-0555; www.cleveldesign.com.
Integrated RTL Design Tool Improves Chip Performance
The DesignWarrior is an integrated register-transfer level (RTL) development environment coupled with automated implementation flows. According to the company, it improves chip performance by guiding design teams to develop better RTL designs.
The DesignWarrior makes performance predictions possible before a single line of RTL is developed and continues refining the prediction until the RTL code is completed. As the design specification evolves, it is automatically mapped directly to a silicon technology. This tool is aware of the logical, synthesis, and physical views of a design, enabling it to determine the points in the hierarchy where the design should be simulated, synthesized, or placed and routed. It automatically sets up the parameters, rules, and constraints based on the estimates derived during the virtual prototyping phase. It also develops time budgets for the blocks in the design and drives the implementation flow.
The DesignWarrior runs on Sun workstations and supports Verilog. Pricing begins at $85,000.
InTime Software Inc., 10131 Bubb Rd., Cupertino, CA 95014; (408) 565-0111; fax (408) 565-0110; www.intime-online.com.