Said to be suitable for all types of high-performance networking infrastructure DSP applications, the MSC8101 digital signal processor with on-chip network interface incorporates the SC140 core architecture. The device is capable of operating at 1,200 MMACS or 3,000 RISC MIPS.
Including a 300 MHz SC140 core, the device includes four arithmetic logic units (ALUs) that provide 1,200 MMACS, a high-performance 150 MHz CPM programmable network protocol engine, 512 KB (256K 16-bit words) of on-chip SRAM, a 100 MHz 64-bit or 32-bit PowerPC bus interface, and a programmable memory controller. In addition, on-chip peripherals such as a 300 MHz enhanced filter coprocessor and a centralized DMA engine are said to enhance performance even further.
Features include four ALUs, a 150 MHz CPM programmable network protocol engine, 512 KB of on-chip SRAM, 100 MHz 64- or 32-bit PowerPC bus interface, and a programmable memory controller. Manufactured using a 0.13 µm copper interconnect process technology, the device operates with a 1.5-V core power and an independent 3.3V I/O power supply. Power dissipation is 500 mW for the entire device. Suggested pricing is under $100 with samples being available in the third quarter of 2001.
Company: MOTOROLA SEMICONDUCTOR PRODUCTS SECTOR (SPS)
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