In a single chip-scale package (CSP) measuring only 1.4-mm in thickness, the company has managed to stack a PSRAM, one SRAM, and two flash memory chips, plus a spacer chip. Employing a proprietary process, the CSP is designed and simulated for thermal and mechanical reliability, as well as to ensure predictable performance. The device targets applications where high memory capacity is needed in a compact design, such as DSPs and ASICs assembled with a controller and stacked memory. In addition, the company has under development a six-chip CSP with the same profile and a 75-µm thick die. For more details, call CHIPPAC INC., Fremont, CA. (510) 979-8220.
Company: CHIPPAC INC.
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