- A next-generation synthesizable MIPS RISC architecture known as Topaz (24K) promises higher throughput and reduced operating power. Developed by MIPS Technologies, the processor core can scale to features below 0.13µ m while maintaining compatibility with the popular MIPS32 architecture. The eight-stage single pipeline in the CPU is optimized for scalable performance and can operate at clock rates from 400 to 550 MHz. The core implements release 2 of the MIPS32 architecture and includes multiple general-purpose register sets and support for vectored interrupts. It also incorporates the code-compression technology with the MIPS16e ASE. Core derivatives based on the Topaz architecture will be available in the fourth quarter of this year, with general licensing starting in early 2004. For more information, go to www.mips.com.
- Taking aim at mobile applications, a pair of fast-cycle DRAMs developed by Fujitsu Microelectronics America Inc. enables digital-camera video data streaming for 3G cellular phones. The MB82DBS02163C and '04163C, which come in 32- and 64-bit Mbit densities, respectively, are the first FCRAMs to incorporate a burst mode for both read and write operations. Both devices are organized with 16-bit interfaces, operate from a 1.65 to 1.95-V supply, and can run with a burst frequency of 66 MHz. Initial access times are 70 ns and clock access times are 12 ns, with a page access time of 20 ns. Active current is 30 mA, while standby current is just 80 µ A for the 32-Mbit device and 120 µ A for the 64-Mbit memory. In lots of 100,000 units, the 32-Mbit chip costs $7, while the 64-Mbit unit goes for $12. For more, go to www.fma.fujitsu.com/fcram