A modified form of synchronous DRAM technology, double-data-rate, fast-cycle random access memory (DDR FCRAM) is primarily focused at the networking market segment. Yet due to its high performance, it also suits such applications as graphics, gaming, and high-end set-top boxes.
DDR FCRAM's innovative architecture combines DRAM-type densities with random cycle times rivaling high-speed SRAMs. A multisourced technology supported by three major memory manufacturers, DDR FCRAM offers fast random cycle time and fast random access time, combined with a conventional DDR interface, to yield a cost-effective, high-bandwidth solution.
This article identifies the main differences and similarities between DDR FCRAM and DDR SDRAM devices. Additionally, it provides controller design guidelines for designers already using a standard DDR SDRAM interface to let them modify their existing designs for DDR FCRAM.
DDR FCRAM architectural enhancements have modified both the conventional DDR SDRAM core and its peripheral logic. This modification includes:
- Core segmentation into smaller memory subarrays for lower power consumption.
- Faster access times and peripheral logic to implement a three-stage row pipeline, enabling simultaneous execution of three commands.
Implementing hidden precharge further reduces the random cycle time (tRC). The three-stage row pipeline contains address-decoder, memory-array, and I/O buffer functions (Fig. 1). To illustrate this pipeline architecture, consider a Read operation: In conventional DRAM technologies, including DDR SDRAM, the memory location is first supplied. Then the data is read into the I/O buffer. Consequently, a conventional DDR SDRAM can't start executing the next address until the current Read Data output is complete.
In contrast, DDR FCRAM can accept a new address once the current address is latched in the decoder. A third address can also be specified once the data of the first address has moved from the memory array to the I/O buffer. This pipeline architecture makes DDR FCRAM ideal for networking applications that require short random cycle times and multibank accesses, such as packet buffering.
Similarities Exist: Even though DDR FCRAM's redesigned core concept offers significantly improved performance over DDR SDRAM, the two share several similar features. This makes it easy for designers to change their designs with minimum effort. The following attributes are common to both DDR FCRAM and DDR SDRAM:
- TSOP 66-pin package
- DDR clocking
- Data strobe signal (DQS) clocking
- four-bank organization
- ×8 and ×16 I/O organization
- 256-Mbit densities
- two and four burst length
- SSTL-2 2.5 V I/O
As mentioned earlier, the architecture of DDR FCRAM has been modified to deliver a faster random cycle time. DDR FCRAM has lower latencies and can handle up to three commands simultaneously. Figure 2 shows this concept. The timing diagram illustrates the differences between a conventional DDR SDRAM and DDR FCRAM. It also reveals the smaller initial latency (tRCD) of DDR FCRAM due to the integrated row address strobe (RAS) and column address strobe (CAS) in the command set. Besides minimizing the latencies, DDR FCRAM operates at a 200-MHz clock rate—delivering the speed needed by high-end networking applications.
Unlike DDR SDRAM, DDR FCRAM doesn't support page-mode operation. Instead, it automatically closes the row and precharges the bank. The device also has a significantly shorter random cycle time (25 ns versus 60 ns for DDR SDRAM).
Moreover, DDR FCRAM can seamlessly operate in the bank-interleave mode. Bus utilization of up to 80% in DDR FCRAM is significantly higher than other DDR DRAM technologies. This higher bus utilization makes the device a suitable replacement for expensive high-speed SRAM technologies.
Controller Considerations: Figures 3a and 3b show memory controller-to-DRAM and the microprocessor-to-memory controller interfaces for DDR SDRAM and DDR FCRAM, respectively. A DDR memory controller can be easily designed to accommodate both DDR SDRAM and DDR FCRAM. The —RAS, —CAS, and —WE pins are replaced by a function pin, FN, and two additional address pins, A13 and A14.
A comparison of functional truth tables for DDR SDRAM and DDR FCRAM command sets shows that the latter is much simpler (see the table). A standard DDR SDRAM has separate signals for command and address: The Active command is issued first, and the row address input takes place at the same clock edge. A Read/Write command and column address follows this. After a specified CAS latency, the Read or Write command is executed.
On the other hand, FCRAM has only two commands: First, an RDA or WRA command is issued, depending on if it's Read or Write (the state of —FN determines Read or Write), then the Lower Address Latch (LAL) command. The RDA and WRA specify the row, column, upper addresses (A0 to A14), and bank addresses, while the LAL completes the Read or Write operation by latching the lower addresses (A0 to A7). This broadside addressing (asymmetrical number of row/column addresses) lets FCRAM achieve faster random access and cycle times. Note that the above comparison is based on a 256-Mbit (×16) DRAM device.
There are other design considerations to address:
Signaling: To take full advantage of FCRAM, the high-speed bus must be able to pipeline addresses. Because a second address can be issued to the FCRAM before the production of the first requested data, an address pipeline must be implemented. DDR SDRAM does not require this.
For ASIC-embedded CPU and controller designs, the ECC, Arbiter, DMAC, memory controller (FCRAM and SRAM), and external-bus interface module must be designed with careful consideration of the following key guidelines for high-performance memory-controller design:
- Activate the memory within one clock cycle.
- Release the high-speed bus before the cycle's end to keep from holding the bus for an extra cycle.
- Use an arbiter to stage bus usage between bus masters and allow priority selection.
- Use burst-increment, decrement, and hold functions.
- Keep the external load to a minimum (few FCRAMs located in close proximity to the ASIC).
Interface And Termination: The interface specification for DDR SDRAM and DDR FCRAM is Stub Series Terminated Logic (SSTL_2), JEDEC standard, JESD8-9. SSTL_2 offers adequate output current drive to permit parallel-termination schemes, which is important for high-speed signaling. It also allows for proper termination of the bus transmission lines and reduces signal reflections. This will improve settling, lower EMI emissions, and make higher clock rates possible. A minimum termination resistance to VTT can be used and still comply with the standard's minimum output voltages and currents.
For best performance when implementing DDR FCRAM, the single-resistor termination scheme is strongly recommended. Benefits include lower cost, simpler signal routing, reduced reflections, and improved signal bandwidth and settling.
DDR FCRAM supports four programmable SSTL_2 drive strengths, which are 4 mA (weakest), 8 mA (default), 12 mA (strong), and 16 mA (strongest). Selection is accomplished by an internal user-programmable register set. This feature allows designers to program the drive strength to suit their overall system and pc-board requirements.
In lightly loaded systems—that is, systems with few memories—where the memories are physically close to the controller, the weakest drive type may be selected to limit the driver slew rates and benefit both signal integrity and radiated emissions. Higher drive currents would better suit heavily loaded systems with more memory devices and higher capacitance.
DQS Termination: The DQS lines should be terminated with discrete resistors to VDDQ and VSS. This will keep noise on VTT caused by the changing data lines from affecting DQS. These lines should be terminated with discrete resistors. This allows the termination to be adjusted independently of any other signals.
Bidirectional Line Termination: The data and DQS lines are bidirectional. To have the same levels at all receivers from all transmitters, a series resistor is required on all devices that can drive the line. The signaling standard is called series stub logic because there's a series resistor at every stub. Terminations to VTT should be at both ends of the main bus. Resistor packs are acceptable for these terminations.
VTT And VREF: The VTT supply must be able to both sink and source current. This means that a standard switching power supply can't be used without a shunt to let the supply sink current. Because each data line is connected to VTT with relatively low impedance, this supply must be very stable.
Designers shouldn't generate VREF with one divider routed from the controller to the memory devices. The optimal solution is to generate a local VREF at each device. Discrete resistors should be used to produce VREF, while resistor packs should be avoided.
Address/Control-Line Termination: Address and control lines (except for DQS lines) are unidirectional. These lines need only a series resistor at the controller. Also, these lines transfer data at half the rate of the data lines and may need less termination to function properly. Resistor packs for these terminations are acceptable.
Frequency Versus Termination: At lower frequencies, the full SSTL termination might not be needed. For point-to-point applications (one controller and one memory device per data line), both the series resistor and the resistor to VTT may often be omitted entirely for frequencies below 160 MHz. Just the series resistor may be required for frequencies under 200 MHz. These termination reductions must be simulated and checked out to ensure that the design has an adequate margin.
Actual driver strength and board layout significantly affect the performance of these termination schemes. Several other schemes have been used successfully in point-to-point applications. The key to successfully implementing FCRAM and achieving peak performance is simulation.
Data Strobe Signal (DQS): Because FCRAM is a DDR-type DRAM, it outputs data at both the rising and falling edges of the clock. In FCRAM, the address and command signals are synchronized with the clock input, while the data pins are synchronized with the DQS signal. Data output takes place at both the DQS's rising and falling edges. DQS is in phase with the clock input of the device.
A lag may occur in the journey time for signals from the controller to the memory, and from memory to the controller due to different wiring lengths of data lines, command/address lines, and the clock (Fig. 4). This lag time makes it difficult for the receiver (memory or controller) to acquire data correctly.
Because the FCRAM performs the input/output of data at twice the frequency of the external clock, the valid data window is narrower. To eliminate this difficulty, the devices (both controller and memory) output the DQS signal. The receiver can acquire data securely by receiving the DQS signal.