EE Product News

Simulator Hews To VHDL-AMS Standard

A prototype single-kernel, mixed-signal simulator is capable of simulating designs based on the new IEEE 1076.1 VHDL-AMS standard. The simulator, developed under a DARPA contract, is an early view into a validated top-down design and simulation environment for mixed-signal and mixed-technology designs. The tool links with the SaberGuide and SaberScope elements of the firm's SaberDesigner tool suite.


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