ASIC suppliers have long noted the advantages FPGAs can offer in getting a solution to market a lot faster than a traditional full-custom design. By combining the advantages of ASIC technology and FPGA technology onto a single chip, traditional ASIC suppliers can deliver high-performance, customizable solutions.
One approach is to treat a block of FPGA logic as a piece of intellectual property (IP). Then, the suppliers can co-integrate the FPGA blocks with the custom circuitry and other IP blocks. That lets them deliver the best of both worlds to system-on-a-chip (SoC) designers.
Another approach might pre-integrate blocks of memory, specialized I/O or timing support (phase-locked loops or delay-locked loops), and large amounts of uncommitted logic. By pre-interconnecting some of the functions on lower layers of metal interconnect and allowing designers to define only the upper two or three layers, fast turnaround times of a week to 10 days can be achieved for megagate ASICs.
Both LSI Logic and Atmel have created many customer-defined ASIC designs that incorporate one or more blocks of configurable FPGA. Other ASIC suppliers are adding FPGA capabilities to their design libraries. When customers design their megagate ASICs, they can set aside various logic portions for last-minute definition using the embedded FPGA blocks and yet go forward with the main portion of the design to meet tight time-to-market deadlines.
Designers at LSI Logic have based their embeddable FPGA blocks on the MSA 2500 programmable logic core developed by Adaptive Silicon. The core provides a datapath-oriented architecture that comes in complexities of up to about 25,000 ASIC gates. Multiple instances of the core can be co-integrated on the ASIC.
One new alternative to Adaptive's MSA core is the HyperLink CCL 18 series developed by newcomer Leopard Logic. The CCL 18 core consists of a more generic FPGA-style architecture based on four-input lookup tables. It includes about 150 kgates of user-configurable logic. The core also can be co-integrated on an ASIC that uses 0.13-µm design rules and five or six levels of metal.
Another company offering a configurable logic core that can be embedded into ASIC designs, eASIC, supplies a building block containing 2048 cells (about 25 kgates). The eASICore was designed for integration into 0.15-µm designs that use seven metal layers. Based on cells that combine a lookup table feeding a D flip-flop, the eASIC cores can deliver performance levels close to that of full ASICs and significantly better than that of FPGAs.
An alternative to FPGAs or full ASIC design was unveiled last month by NEC. The company has crafted a concept dubbed Instant Silicon Solution Platforms—a series of predefined chips that contain various logic and function resources and can be customized by defining only the top two layers of the five-layer metallization interconnect. The lower three layers are predefined and used to implement the dedicated blocks of logic and memory. Only two levels of metal must be defined, so the chips (wafers) can be premanufactured up through the third level of metal and kept on the shelf. Just a week to 10 days are needed to add the last two metal layers' final customization.
The first devices defined in the family are based on the company's 0.13-µm process. They contain from 227,000 to 1.1 million gates, plus 256 kbits to 1 Mbit of configurable static RAM (64 blocks of 16 kbits each). Yet unlike traditional gate arrays that use NAND gates as the basic logic building block, NEC's designers moved up one level and used a more complex logic building block that contains combinatorial or sequential elements (see the figure).
The chips also pack four analog PLLs, another four digital delay-locked loops, and several predefined clock domains. To ease the testing of these arrays, the designers added multiple embedded testing capabilities—boundary scan, built-in self-test, multi-scan, and a test bus. Future versions of the ISSP family will include on-chip 32-bit processors and high-speed serial interfaces (3.125-Gbit/s SERDES ports).
Though they hit a peak capacity of about 550k ASIC gates (equivalent to about 2 million FPGA gates) without the same resources, the Chip Express CX4551 masterslice and the Lightspeed Semiconductor Modular Arrays boast turnaround times comparable to the NEC ISSP devices. Like the ISSPs, just the upper two or three metal layers on the arrays have to be deposited to complete the masterslices' configuration. The top-of-the-line CX4551 includes 448 kbits of embedded SRAM, while the largest Lightspeed device will pack 896 kbits.
Another company trying to get a piece of the FPGA market, AMI Semiconductor, has teamed with Taiwan Semiconductor Manufacturing Co. (TSMC) to produce a prefabricated family of arrays that just need the upper metal layers deposited to complete the design. TSMC will fabricate the silicon using its 0.18-µm design rules. AMI will do the final metallization based on the netlists supplied by the customers.
The AMI arrays are somewhat similar to the NEC ISSP family. The AMI XpressArrays will provide densities of up to 2.6 million gates; up to 1.4 Mbits of embedded, configurable SRAM; four analog PLLs; a dozen DLLs; and a wide variety of I/O options, including differential interfaces.