Once considered just a logic replacement for small- and medium-scale logic devices, the field-programmable gate array (FPGA) has come into its own as a total system solution. It can replace anything from a few gates to a full custom system-on-a-chip (SoC) ASIC. Advances in silicon fabrication and metallization systems now let the highest-density FPGAs pack over 5 million system gates, several million bits of static RAM, and system support functions such as CPUs, high-speed serial interfaces, and much more.
Most FPGAs are built around SRAM-based configurable cells, such as those offered by Altera and Xilinx on their Stratix and Virtex families. Yet these solutions require an external nonvolatile memory to hold the configuration pattern. As a result, they require a few milliseconds to hundreds of milliseconds for configuration when power is turned on.
Alternative approaches for the configurable cells employ either flash-based reprogrammable cells or one-time programmable antifuse cells. Because the configuration data is already on the FPGA chip, configuration time can be measured in microseconds. In addition, no external configuration memory is required, which eliminates a chip from the bill of materials.
Flash-based cells are employed on the ProASIC families from Actel and the iSPGAL and iSPXPGA from Lattice Semiconductor. Antifuse elements populate the Acellerator and other families offered by Actel, as well as the pASIC family from QuickLogic. Lattice and Quicklogic also have families of SRAM-based FPGAs. These SRAM-based FPGAs target low-power, moderate-density applications.
FPGAs DISPLACE TRADITIONAL ASICs
When FPGAs started to come into their own, gate arrays provided the main competition. Gate arrays offered a lower cost per chip in volume applications and only required a few metal masks to configure the logic.
As FPGAs got larger, though, they absorbed most of the market for gate arrays and started to give even low-complexity cell-based designs some stiff competition. As the cost of fabricating cell-based ASICs continues to skyrocket, FPGAs become more attractive due to their near-zero nonrecurring engineering costs. However, the resource-rich, multimillion-gate FPGAs aren't cheap. In small quantities, the largest versions can sell for several thousand dollars each.
The disparity in cost between FPGAs and the nonrecurring engineering (NRE) overhead of cell-based ASICs has opened a market window for what are called structured ASICs and platform ASICs. These partially premanufactured ASICs contain resources similar to those of FPGAs (logic gates, memory, clock trees, standard and high-speed I/Os, etc.). But they use metal layers to configure the logic. Therefore, they incur moderate NRE costs.
In addition to a potential cost advantage when used in moderate volume, the structured and platform ASICs can usually deliver higher performance than FPGAs. The chips may be fabricated with the same process rules as FPGAs. But prediffused logic on most structured and platform ASIC chips doesn't suffer the overhead of the RAM-based lookup tables used in the SRAM-based FPGAs. Thus, functions implemented on the structured and platform ASICs can usually run at higher clock rates than their FPGA counterparts.
As FPGAs attack the high end with larger and, usually, costlier chips, FPGA suppliers are looking at ways they can reduce the cost of the chips. Then they would become attractive in high-volume applications such as consumer products and automotive systems.
To this end, both Altera and Xilinx have developed families of flash- and SRAM-based FPGAs (the Max II and Cyclone families from Altera and the Spartan 3 and EasyPath approach from Xilinx) that enable them to price their lowest-density family members at less than $4/chip in large quantities (for a device with about 50,000 system gates). Later this year, Actel also plans to release a new family of aggressively priced flash-based FPGAs.
To handle high-end SoC applications, the FPGAs must be able to deliver the performance needed to handle the application. Plus, they've got to supply the desired level of integration to reduce the component count and implement complex functions that might otherwise require a custom ASIC. The latest FPGAs from Xilinx, Altera, and Actel meet such expectations.
The recently unveiled Virtex 4 series from Xilinx is actually several families of FPGAs that share a common architectural approach called ASMBL (advanced silicon modular blocks). Rather than offer a single generic set of chips with a span of gates, memory, and other resources, the company defined three sets of chips.
One set is optimized for general compute-bound applications, another for DSP-intense applications, and a third for communications-related applications—the LX, SX, and FX, respectively. By creating three different base feature sets, Xilinx tries to provide FPGAs that better match the customer's applications, as well as deliver higher performance and logic efficiency.
All three families share some common features—500-MHz digital clock managers, phase-locked clock dividers, and multiple on-chip differential clock-distribution networks. Also common to all of the chips are blocks of SmartRAM that include integrated FIFO control logic, 1-Gbit/s I/O pads with the company's ChipSync source-synchronous technology, and the company's XtremeDSP slices that contain multiplier-accumulators.
A new logic fabric is the basis for improved performance of Altera's Stratix II family. The FPGAs hike performance by about 50% over the company's previous Stratix family, while delivering higher resource efficiency and consuming about half the power. The largest member in the family packs about 4 million system gates; almost 10 Mbits of memory; 384 18- by 18-bit multipliers to assist in DSP-intense applications; and 12 phase-locked loops to provide multiple, independent clocks.
IP—A KEY ELEMENT
No matter which FPGA you select, one crucial aspect of system design is the availability of key blocks of intellectual property (IP) that can be merged into your logic design. Although FPGA vendors have already created large libraries of IP, both internally developed and available from third-party developers, the need for fresh blocks of IP never goes away.
New system interfaces or functions must continually be added to reduce the burden on system designers, and of course, provide FPGA vendors with an "edge" to attract more customers. Large blocks such as MPEG decoders, double-data-rate memory controllers, PCI bus interfaces, specialized filter blocks, and many others are the latest jewels to be added.
Embedded processors are also key elements that designers need on FPGAs, rather than add a separate microcontroller or 32-bit processor. Many popular 8-bit microcontrollers are available from various sources, but Altera and Xilinx both crafted their own logic-efficient 16- and 32-bit soft-core embedded processors (the NIOS and microBlaze, respectively). In its Virtex II and 4 families, Xilinx embedded two PowerPC hard cores into the silicon. The hard cores can deliver 50% or better performance than an equivalent soft-core based CPU.