Today, the accepted design methodology for high-level ASIC design consists of capturing design intent with a hardware description language (HDL) at the register-transfer (RTL) or behavioral level. The design is then verified with an HDL simulator and synthesized to the gates. Yet this hasn't always been the case.
Gate-level design once was typical. But when the average ASIC design passed the 10,000-gate threshold, gate-level design methodologies began to break down. And, the pressure to reduce design cycles increased. As a result, high-level design became an imperative part of maintaining competitiveness. This same trend is now repeating itself in field-programmable-gate-array (FPGA) design.
With design complexity on the rise and high-level design tools becoming more readily available, the FPGA market is poised for widespread adoption of high-level design methodologies. In fact, most analysts and industry experts agree that tens of thousands of FPGA designers will turn to high-level design methodologies in the near future. This transition stems in part from the technology advances that have taken place in the electronic-design-automation (EDA), hardware, and software industries that have occurred over the past five to 10 years.
To meet the unique requirements of FPGA designers, an effective FPGA high-level design methodology must leverage these technologies. Contrary to popular opinion, the EDA industry hasn't been waiting for FPGA designers to catch up to high-level design methods. Instead, it's been waiting for high-level design solutions to catch up to the needs of FPGA designers.
While high-level design might not be right for everyone, it's certainly easy to understand its appeal. At densities of 10,000 gates or less, it's relatively easy to visualize the functionality of an FPGA design by analyzing its schematic. But when design densities begin to surpass the 20,000, 50,000, and 100,000-plus gate-level mark, ensuring that a design will work simply by looking at the schematic becomes impossible.
HDL use allows the designer to organize and programmatically analyze highly complex designs with tools like HDL simulators. In other words, simulation-result analysis for functional design verification has replaced schematic visual inspection.
FPGA designers making the switch to a high-level design methodology enjoy some obvious benefits. First, individual designers are able to handle increased complexity by working at higher levels of abstraction and delaying implementation details to a largely automated back-end process. Second, designers can shorten cycles and improve quality by verifying functionality earlier in the design cycle, when design changes are easier and less expensive to make. These benefits also drove ASIC designers to high-level design.
Making the transition to a new design methodology is never easy. There are always obstacles on the way to adoption. The migration path to a high-level design methodology for FPGA design is no exception to the rule.
One barrier that hampers the adoption of this methodology is the common misconception that FPGA designers require significantly less functionality and features in their design software than ASIC designers. The truth is that they face the same time-to-market pressures and deadlines as their ASIC counterparts. FPGA designers will use as many features and as much functionality as is made available to them. These can include advanced debugging capabilities like data-flow analysis, complete VHDL or Verilog language coverage, or leading-edge simulation and compilation performance.
Traditionally, the tools available to FPGA designers have been newcomers or "also-rans" that didn't have the quality and functionality to compete in the ASIC design-tool market. This trend must change. Today, each component of an FPGA HDL tool suite must be a leader in its class with a clear path to increased levels of functionality equal to, or approaching that of, ASIC design tools.
Another impediment that must be overcome is the economic difference between what the ASIC designer pays for tools and what the FPGA designer can afford to pay for them. While ASIC design-seat software traditionally runs over $100,000, companies rarely spend more than $10,000 for an FPGA design seat. So, EDA vendors hoping to serve the FPGA market must be structured to field products with price/functionality ratios considerably lower than what they sell to the ASIC market.
This economic requirement seems at odds with the needed functionality and flexibility. Still, highly focused, efficient organizations are delivering these solutions today.
Providing high value in design software takes commitment to organizational efficiency on the tool vendor's part. Keeping organizations small and focused is critical to reducing overhead. Also, companies that are innovative in the areas of electronic commerce, electronic software distribution, and low-cost distribution channels can further reduce their costs and pass these savings on to customers in the form of lower prices.
Of course, finding a way to help FPGA designers make the leap to HDL-based design without missing a beat in productivity also is key to gaining acceptance. Many tool vendors have responded with simplified tools, but that's not enough. Vendors must provide training that can lead FPGA designers into increasing levels of expertise at their own pace. The combination of easy-to-use tools and adequate training will ultimately help smooth the transition.
Changing Over to HDL
At the high end of the FPGA market, the design methodology has begun to mirror an ASIC design methodology. Many current FPGA design starts are larger and more complex than what ASIC designers were doing as recently as two years ago. To meet the changing needs of FPGA designers, tool vendors must provide solutions that will enable FPGA designers to not only deal with complex designs, but also help them make the transition to HDLs as painless as possible.
As FPGA designers begin to move to HDL design tools such as simulators and graphical entry tools, they undoubtedly will face the challenge of deciding which tools to purchase. They also will have to figure out who their supplier will be. These decisions should be made based on the following criteria:
- Does the vendor have close partnerships with the FPGA vendors?
- Does the vendor offer excellent support?
- Is this a proven product with robust, scalable technology?
- Is the product flexible?
This last point is a broad requirement with many implications. Depending upon the experience of the designer and the complexity of the design, a simple push-button development flow may be sufficient. In fact, it may be preferable to a highly configurable, highly optimized development flow. With a push-button configuration, all the FPGA tool-suite elements are integrated. This enables even novice HDL users to get working silicon much faster.
As developers gain experience with HDL tools, more control and optimization—such as batch simulation scripting and control of performance optimization levels—are required. In this case, simplistic "push-button-only" tools are quickly outgrown. Also, some designers are content to use a packaged, integrated tool suite while others want or need to mix and match point tools. A leading-edge FPGA tool suite must provide both types of operation, allowing the user to begin at a basic level and progress to a more sophisticated level of operation as needed.
No one has ever said that the transition to a high-level design methodology for FPGA design was going to be easy. Fortunately, HDL-based design has been around for a long time, and the process is now well-established and proven.
Commonly recognized steps in an HDL-based design flow include design entry, RTL simulation, synthesis, functional simulation, place and route, gate-level timing simulation, and test-bench generation (Fig. 1).
Fundamentally, each cell (lowest level object) in a design must have an HDL model available which mimics that cell's functionality. These models are usually packaged into libraries that are made available by the different FPGA vendors in either source and/or binary form.
Once the models are in hand, the next step is to create the design. To convert an existing schematic design, the FPGA designer must follow the following steps:
- Most schematic capture packages have an "export to VHDL or Verilog" capability. This will write out the VHDL or Verilog HDL code of the user's schematic. Information about how the cells in the design are connected is contained in this HDL code. The code also will contain information about what libraries are needed for the cells used in the design.
- Compile the FPGA-provided cell library, or use a precompiled one if available.
- Compile the HDL design from the schematic export.
- Simulate the compiled HDL design. This is accomplished by applying input stimulus to the design and analyzing the simulation results to verify that the design is operating correctly.
On the other hand, if the FPGA designer is starting from scratch with no pre-existing schematic available, there are two options to create the design. First, it can be constructed by hand, using a text-editor to write the HDL code directly. The other option is for the designer to employ a graphical entry tool to enter the design using a block diagram, state-machine, flow-chart, or table-entry editor.
With graphical HDL entry, FPGA designers can capture their high-level design in schematic-like block diagrams and specify functionality either directly in HDL or through state diagrams or truth tables. This approach relieves designers of much of the programming inherent in HDL design. For example, a block-diagram editor can generate all the HDL code necessary to glue the entire design together. It can also provide code that will allow communication between modules and with the test bench. This "overhead" code is typically the most frustrating aspect of learning how to use an HDL, and it often gets in the way of allowing designers to specify actual functionality. Providing FPGA designers with automated code generation will accelerate their adoption of HDL-based tools.
Once the design is created, it must be verified prior to the RTL to ensure that its functionality is as intended. At this point, the test bench should be created (Fig. 2). It will be used throughout the FPGA flow to verify the functionality of the design at the RTL level and the functional and timing gate levels.
A test bench is a separate set of VHDL or Verilog code that is connected to the design's inputs and outputs. Since these stay constant through synthesis and place and route, the test bench can be used at each stage to verify functionality.
The test bench has two purposes. It provides the stimulus and response information, such as clocks, reset, and input data, that the design will encounter when implemented in an FPGA device and installed into the final system. Also, it contains regression-checking constructs that allow key functionality to be tested throughout the FPGA HDL simulation flow.
The Cost Of The HDL Payoff
Test benches often contain the most complex HDL code in the design. An investment in learning VHDL or Verilog beyond just the basics will pay off greatly here. These intelligent test benches can be used to significantly enhance the designer's productivity in developing unit and system tests.
HDL-based design represents a new paradigm for some FPGA designers. The steps involved are straightforward, but like anything else that's worth doing, it requires going through a learning curve.
For example, FPGA designers must learn how to use an HDL compiler—a tool used to convert the HDL design into an executable representation. Most HDL compilers make this easy by providing defaults for compile options and easy-to-use graphical user interfaces. But if the HDL compiler or simulator produces error messages, the user must know how to determine what they have done wrong in the HDL design. Quality tools simplify this task by allowing the user to double click on the compiler message to link directly to the offending source code.
Designers also must learn to fully exploit the power of HDLs. Designing at a higher level of abstraction and then allowing the synthesis tool to produce an actual implementation requires faith in both the tools and the processes. The good news is that the HDL-based design process has already been well proven by literally thousands of designers.
As tool vendors have begun to address the unique requirements of FPGA designers, high-level design has finally come of age. Designers and engineering managers considering a switch to HDL-based FPGA design now have a variety of tools at their disposal from which to choose.
Selecting the appropriate tools is not a decision made on price considerations alone. Rather, designers must evaluate which tools are leaders in their class, offer upward mobility to higher levels of flexibility and functionality, and speed up the HDL learning curve.
Regardless of which tools you use, the bottom line is simple—advanced HDL design tools are a must for FPGA and ASIC designers alike.