Algorithmic synthesis—the efficient implementation of algorithms in silicon—offers compelling value to both system-on-a-chip (SoC) and FPGA design teams. However, there are subtle but important differences in the teams’ requirements when using algorithmic synthesis tools. This is especially true for FPGAs, which can be designed as just one in a series of steps to creating an SoC or as production-ready devices.
The different requirements and different expertise of each team lead to different demands on the synthesis tools. In both SoCs and FPGAs, the algorithms define and differentiate the end product. Algorithmic synthesis is used to deliver efficient hardware implementations of these algorithms in silicon to create the key PPA (performance, power, and area) characteristics. There are two main uses for algorithmic synthesis tools when applied to FPGAs:
• FPGA design: the development of a device that will be directly used in a final product. The applications for FPGA design include high-end TVs, wireless basestations, and medical imaging systems. FPGA-dedicated design teams complete these designs.
• “FPGA prototyping”: the use of an FPGA to assist in verifying the RTL to be implemented on an SoC. In this case, the FPGA primarily is used to verify the SoC RTL, with the results considered in relation to the SoC design. The inefficiency of the FPGA implementation itself isn’t a major consideration. The needs for SoC designers using FPGA prototyping are the same as for the rest of the SoC.
Differences in Hardware Experience
SoC design teams tend to have a significant number of hardware design engineers because they have to purchase or develop processor, communication and control, and memory blocks to build the SoC platform before they start implementing the algorithms in silicon by hand.
The FPGA vendor provides FPGA design teams with the processor, communication and control, and memory blocks. The team is responsible for developing the critical functionality of the algorithms in silicon. As a result, FPGA design teams are usually smaller, with only limited access to hardware expertise.
Differences in Business Imperatives
For SoC teams, the business imperative is to meet the PPA targets on time, with the same size or smaller teams, in the face of growing design complexity. Historically, these teams implemented the algorithms in silicon by hand. But today, they struggle to meet tapeout dates and remain responsive to late changes in specifications.
Algorithmic synthesis tools offer many proven benefits to an SoC design team, enabling the hardware engineer to explore, design, and verify algorithms in silicon more efficiently and rapidly than manual design methods. Teams are concerned that the PPA from the synthesis tools compare favorably with their existing manual designs and/or their current estimates while reducing design cost and time.
Additionally, the teams already have a set of users trained on implementing algorithms in silicon manually. They may have questions surrounding verification, integration, and the ability to manage engineering change order (ECO) types of changes. An experienced algorithmic synthesis vendor can lead them through the process, focusing on optimal benefits and minimized risk.
For FPGA design teams, the business imperative is to find a cost-effective method of implementing the algorithms with their current team. As the cost per unit function of FPGAs continues to tumble, it makes good financial sense to implement functionality in an FPGA rather than in a DSP. However, the lack of hardware expertise in these teams means this can only happen if the tools for building efficient hardware from an algorithm can be employed without detailed hardware knowledge.
FPGA teams are primarily concerned with getting good results, achieving performance targets, and fitting the FPGA into a device that meets their cost requirements with their current team members. There is no mask set, and changes can be implemented very rapidly and without extra cost. The major consideration for the team is whether the designers can be effective and find a financially viable solution in terms of the cost of the FPGA device.
The Solution for Both
SoC and FPGA design teams both want a tool that can implement complex algorithms efficiently in silicon. The tool must demonstrate the ability to meet PPA targets and delivery deadlines. It also must be highly responsive to changes in specifications that occur late in the design cycle.
Algorithmic synthesis has proven itself to be a viable solution for both SoC and FPGA applications. Using algorithmic synthesis is more about “when” rather than “if.” The issue is not whether algorithmic synthesis works but how to get optimal results while minimizing risk.
Algorithmic synthesis has a very bright future in both domains. Both SoC and FPGA-based products will continue to push performance, power, and cost to survive and thrive in competitive markets. There are now multiple providers of algorithmic synthesis tools and many examples of multiple design teams having used algorithmic synthesis in production designs.
We are just seeing the beginning of serious deployment of algorithmic synthesis in both domains. Today, there is the possibility of confusion, because although some requirements for SoC and FPGA development are similar, many are different. In the future, we will see more clearly delineated differences as both market segments show their separate requirements. In both cases, we look forward to the opportunity and challenge.